UPD705102 datasheet(33/80 Pages) NEC

33 / 80 page

µPD705102

Data Sheet U13675EJ2V1DS00

13. STANDBY FUNCTION

The V832 has the following two modes as standby functions:

• Power management mode

• Standby mode

(1) Power management mode

The following two power management modes can be used. According to the combination of these modes, the

operating frequency is actively changed.

• PLL mode

This is the mode normally used. In this mode, the oscillation clock of the external input clock/OSC, which is

expanded 6 or 8 times by the PLL synthesizer, is employed as the CPU clock.

• Direct mode

In this mode, the oscillation clock of the external input clock/OSC is employed as the CPU clock without passing

through the PLL synthesizer.

(2) Standby mode

The following two standby modes can be used.

• HALT mode

In this mode, the clock generator (oscillator and PLL synthesizer) operates, but the operating clock of the CPU

is stopped. The other internal peripheral functions are supplied with the clock and continue operation. By using

this mode in combination with the normal mode, the power consumption of the entire system can be reduced.

• STOP mode

This mode stops supply of the clock to the CPU and peripheral I/O.

It can reduce the power consumption much more than the HALT mode.

Clock output of PLL synthesizer

• In PLL mode:

Operation of the PLL can be started or stopped by the PLLSS bit of the power management

• In direct mode: The PLL always stops.

Table 13-1 shows the operation of the clock generator in each mode.

UPD705102 Datasheet(PDF) 33 Page - NEC