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UPD705102 Datasheet(PDF) 21 Page - NEC |
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UPD705102 Datasheet(HTML) 21 Page - NEC |
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21 / 80 page  µPD705102 21 Data Sheet U13675EJ2V1DS00 Receive buffer RXB0 RXB0L Receive shift register 16/8 RXD Receive control parity check TXD 1/16 Status register 8 ASIS0 Transmit shift register TXS0 TXS0L Transmit control parity append 1/16 1/2 Mode register ASIM00 ASIM01 SEL INTSER INTST INTSR Baud rate generator φ Internal peripheral I/O bus 8 16/8 The configuration of the asynchronous serial interface (UART) is shown below. Figure 9-1. Block Diagram of UART Remark φ = bus clock : 48 M to 1.3 MHz: @input clock 6× : 36 M to 0.73 MHz: @input clock 8 × |
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