Block descriptions

UM0805

10/29

Doc ID 16304 Rev 3

6.3

External FPGA subsystem (optional)

This block includes an FPGA (Xilinx Virtex4 LX60) plus its Flash memories and the JTAG

interface for programming it. The FPGA is connected to the SPEAr600 through a proprietary

bidirectional bus. This enables the development of IPs in the FPGA. In this way the FPGA

can be used as an expansion of the system. When the FPGA is present, 112 additional I/O

lines are provided on the expansion connector (J1). A dedicated clock input line for the

FPGA is also connected to socket U4 where an external oscillator can be installed if a

special clock frequency needs to be input to the FPGA. The oscillator output can be enabled

or disabled using switch SW2-4.

The interface between the FPGA and the SPEAr600 can be synchronous or asynchronous.

Its speed can also be set independently from the system speed. This means that, even with

this interface is running at 60~80 MHz (which can be considered as a reasonable speed) all

the other blocks of the SPEAr can still work at their maximum frequency.

6.4

Ethernet subsystem

This subsystem is based on the Ethernet GMII PHY DP83865 (U14) and a connector that

also includes all the required magnetics. Several configuration jumpers are present and also

several LEDs to display the line status/activity.

6.4.1

Configuration jumpers and switches

Note:

When DIP switch SW4-x is in the ON position, the bit value is 0. When the DIP switch is in

the OFF position, the bit value is 1.

Table 1.

Switch 4 configuration

Bit

Description

1

PHY Address bit 1 (default value = 0)

2

PHY Address bit 2 (default value = 1)

3

PHY Address bit 3 (default value = 0)

4

PHY Address bit 4 (default value = 0)

5

Multiple Node Enable: This pin determines if the PHY advertises Master (multiple

nodes) or Slave (single node) priority during 1000BASE-T Auto-Negotiation.

1: Selects multiple node priority (switch or hub).

0: Selects single node priority (NIC) (default value).

6

Auto MDIX Enable: This pin controls the automatic pair swap (Auto-MDIX) of the

MDI/MDIX interface.

1: Enables pair swap mode.

0: Disables the Auto-MDIX and defaults the part into the mode preset by the

MAN_MDIX_STRAP pin (default value)

7

Clock To MAC Enable:

1: CLK_TO_MAC clock output enabled (default value)

0: CLK_TO_MAC disabled

8

Not used.