AN4206 datasheet(12/34 Pages) STMICROELECTRONICS

12 / 34 page

Power supplies

AN4206

12/34

DocID023944 Rev 4

The switch to the VBAT supply is controlled by the power down reset (PDR) circuitry

embedded in the Reset block.

If no external battery is used in the application, it is highly recommended to connect VBAT

externally to VDD.

1.1.4

Voltage regulator

The voltage regulator is always enabled after reset.

It works in three different modes depending on the application modes:



Run mode: the regulator supplies full power to the 1.8 V domain (core, memories and

digital peripherals)



Stop mode: the regulator supplies low power to the 1.8 V domain, preserving the

contents of the registers and SRAM. In Stop mode, the voltage regulator can be

configured in low power mode in order to further reduce the consumption.



Standby mode: the regulator is powered off. The contents of the registers and SRAM

are lost except for the Standby circuitry and the Backup domain. This includes the

following features which can be selected by programming individual control bits:

–

Independent watchdog (IWDG): the IWDG is started by writing to its Key register

or by a hardware option. Once started it cannot be stopped except by a reset.

–

Real-time clock (RTC): configured by the RTCEN bit in the Backup domain control

–

Internal RC oscillator (LSI): configured by the LSION bit in the Control/status

–

External 32.768 kHz oscillator (LSE): configured by the LSEON bit in the Backup

domain control register (RCC_BDCR).

AN4206 Datasheet(PDF) 12 Page - STMicroelectronics