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PCM1865DBT Datasheet(PDF) 58 Page - Texas Instruments |
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PCM1865DBT Datasheet(HTML) 58 Page - Texas Instruments |
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58 / 115 page  VINR3 / VIN3P 30 VINL3 / VIN4P 29 VINR4 / VIN3M 28 VINL4 / VIN4M 27 1 VINL2 / VIN1M 2 VINR2 / VIN2M 3 VINL1 / VIN1P 4 VINR1 / VIN2P 5 Mic Bias 6 VREF 7 AGND 8 AVDD 9 XO 10 XI 11 LDO 12 DGND 13 DVDD 14 IOVDD 15 SCKI (3.3V) Stereo Pair Stereo Pair Stereo Pair Stereo Pair Digital Output Bit Clock Left / Right Clock Note : Pins not shown in specific order 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF DOUT 18 BCK 17 LRCK 16 MD0 26 MISO/GPIO0/DMIN2 22 GPIO1 / Int A / DMIN 21 GPIO2 / Int B / DMCLK 20 GPIO3 / Int C 19 AD 25 SDA 23 SCL 24 I2C Bus Interrupt / GPIO I2C Select I2C Address Select GND 1.8V 2.2 mF 2.2 mF GND 4.7 mF GND 3.3V PCM1861, PCM1863, PCM1865 SLAS831C – MARCH 2014 – REVISED AUGUST 2014 www.ti.com Typical Applications (continued) 9.2.2 PCM1863 with 3.3V AVDD, DVDD , 1.8V IOVDD, BCK Input Slave PLL Figure 58. Simplified Schematic, PCM1863 I2C Controlled Subsystem 9.2.2.1 Design Requirements • Device control method: Software control by I2C • Clock slave to a 1.8V device that only supplies BCK and LRCK (such as a Bluetooth Module) • Single-ended analog inputs 9.2.2.2 Detailed Design Procedure • Device control method: Configure for I2C by Pulling MD0 to GND, and setting I2C address by setting the AD pin High or Low • Ensure that BCK is configured in clock master device to be 64×fS for automatic PLL setting to function. • Single-ended analog inputs – MD2, MD5, MD6 configuration - see Table 2 • Audio slave mode – Configure appropriate clock registers – Page.0 0x20 - Set MST_MODE=1 (I2S Slave) • The power rails in this application allow the usage of X7R Ceramic capacitors. A maximum voltage rating of 6.3V should be enough for the power supply capacitors. 58 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: PCM1861 PCM1863 PCM1865 |
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