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PCM1865DBT Datasheet(PDF) 65 Page - Texas Instruments |
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PCM1865DBT Datasheet(HTML) 65 Page - Texas Instruments |
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65 / 115 page  Combined AGND + DGND Copper Pour 5 Mic Bias MD5 / GPIO1 / Int A / DMIN 20 MD4 / MISO / GPIO 0 / DMIN2 21 MD3 / MC / SCL 22 DOUT2 / MD2 / MOSI / SDA 23 MD1 / MS / AD 24 MD0 25 VINR3 / VIN3P 30 VINL3 / VIN4P 29 VINR4 / VIN3M 28 VINL4 / VIN4M 27 1 VINL2 / VIN1M 2 VINR2 / VIN2M 3 VINL1 / VIN1P 4 VINR1 / VIN2P 6 VREF 7 AGND 8 AVDD 9 10 11 12 13 14 15 SCKI (3.3V) 26 LRCK DOUT 17 BCK 16 MD6 / GPIO2 / Int B / DMCLK 19 INT / GPIO3 / Int C 18 XO XI LDO DGND DVDD IOVDD P Analog Digital PCM1861, PCM1863, PCM1865 www.ti.com SLAS831C – MARCH 2014 – REVISED AUGUST 2014 11 Layout 11.1 PCM186x Grounding and System Partitioning Designers should try to use the same ground between AGND and DGND to avoid any potential voltage difference between them. On the PCM186x EVM, we achieve up to 110dB SNR using a single ground plane, and ensuring that the return currents for digital signals do not go near the AGND pin or the input signals. Avoid running high frequency clock and control signals near AGND, or any of the VIN pins where possible. The pin layout of the PCM186x partitions into two parts - analog section and digital section. Providing the system is partitioned in such a way that digital signals are routed away from the analog sections, then no digital return currents (for example, clocks) should be generated in the analog circuitry. Figure 66. Single Ground with Analog Partitioned to the top, Digital at the bottom With this in mind, when we laid out the EVM, we made sure that any digital return currents had a ground plane to their source/destination that didn't require passing below any analog circuitry. shown in Figure 67 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 65 Product Folder Links: PCM1861 PCM1863 PCM1865 |
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