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PCM1865DBT Datasheet(PDF) 13 Page - Texas Instruments

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Part # PCM1865DBT
Description  PCM186x 110dB 2ch and 4ch Audio ADCs with Universal Front End
PDF  115 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

PCM1865DBT Datasheet(HTML) 13 Page - Texas Instruments

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background image
SDA
SCL
START
Repeated
START
STOP
t
BUF
t
S-HD
t
SCL-F
t
D-SU
t
D-HD
t
LOW
t
SCL-R
t
HI
t
RS-SU
t
RS-HD
t
SP
t
SDA-R
t
SDA-F
t
P-SU
PCM1861, PCM1863, PCM1865
www.ti.com
SLAS831C – MARCH 2014 – REVISED AUGUST 2014
6.10 I
2C Control Interface Timing Requirements
PARAMETER
CONDITIONS
MIN
MAX
UNIT
Standard
100
kHz
fSCL
SCL clock frequency
Fast
400
kHz
Standard
4.7
µs
tBUF
Bus free time between a STOP and START condition
Fast
1.3
Standard
4.7
µs
tLOW
Low period of the SCL clock
Fast
1.3
Standard
4.0
µs
tHI
High period of the SCL clock
Fast
600
ns
Standard
4.7
µs
tRS-SU
Setup time for (repeated) START condition
Fast
600
ns
tS-HD
Standard
4.0
µs
Hold time for (repeated) START condition
tRS-HD
Fast
600
ns
Standard
250
ns
tD-SU
Data setup time
Fast
100
Standard
0
900
ns
tD-HD
Data hold time
Fast
0
900
Standard
20 + 0.1CB
1000
ns
tSCL-R
Rise time of SCL signal
Fast
20 + 0.1CB
300
Standard
20 + 0.1CB
1000
ns
Rise time of SCL signal after a repeated START condition and after an
tSCL-R1
acknowledge bit
Fast
20 + 0.1CB
300
Standard
20 + 0.1CB
1000
ns
tSCL-F
Fall time of SCL signal
Fast
20 + 0.1CB
300
Standard
20 + 0.1CB
1000
ns
tSDA-R
Rise time of SDA signal
Fast
20 + 0.1CB
300
Standard
20 + 0.1CB
1000
ns
tSDA-F
Fall time of SDA signal
Fast
20 + 0.1CB
300
Standard
4.0
µs
tP-SU
Setup time for STOP condition
Fast
600
ns
CB
Capacitive load for SDA and SCL line
400
pF
tSP
Pulse width of spike suppressed
Fast
50
ns
VNH
Noise margin at High level for each connected device (including hysteresis)
0.2VDD
V
Figure 3. I2C Control Interface Timing
Copyright © 2014, Texas Instruments Incorporated
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Product Folder Links: PCM1861 PCM1863 PCM1865



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