PCM1865DBT datasheet(21/115 Pages) TI

21 / 115 page

PCM1861, PCM1863, PCM1865

www.ti.com

SLAS831C – MARCH 2014 – REVISED AUGUST 2014

8.6 PCM1861 Input Multiplexer

The hardware controlled devices can support a wide gain range using the MD2, MD5 and MD6 configuration pins

as follows:

Table 3. Channel and Gain Selection for Hardware Controlled Devices

MD6

MD5

MD2

ADC1_L / PGA1_L

ADC1_R / PGA1_R

S.E - VINL1 / 0 dB

S.E - VINR1 / 0 dB

S.E - VINL2 / 0 dB

S.E - VINR2 / 0 dB

S.E - VINL3 / 0 dB

S.E - VINR3 / 0 dB

S.E - VINL4 / 0 dB

S.E - VINR4 / 0 dB

S.E - VINL4 / 12 dB

S.E - VINR4 / 12 dB

S.E - VINL4 / 32 dB

S.E - VINR4 / 32 dB

DIFF(VIN1P/VIN1M) / 0 dB

DIFF(VIN2P/VIN2M) / 0 dB

DIFF(VIN3P/VIN3M) / 12 dB

DIFF(VIN4P/VIN4M) / 12 dB

8.7 PCM1863/5 Mixers and Multiplexers

The PCM186x software programmable devices offer a mix/multiplex level of functionality on the front end as

shown in Figure 20. The switches integrated into the multiplexer can also be switched on in parallel, offering a

direct

mix

inputs.

This

function

can

selected

for

each

ADC

input

selection,

ADCX1_INPUT_SEL_X (Page.0, 0x06

→ 0x09). In single ended mode, each Audio ADC is tightly coupled to a

dedicated PGA and MUX. ADC1L (and ADC2L on the PCM1865) is connected a mux that has input pins VINLx,

(x = 1 to 4). ADC1R (and ADC2R on the PCM186) is connected to a mux that has input pins VINRx (x = 1 to 4).

Mixing between the left channels of stereo pairs is possible in the mux dedicated to ADC1L and right channels of

stereo pairs in the mux dedicated to ADC1R. In addition, polarity of the inputs can be inverted using the MSB of

the select register. Mixing left and right sources to create mono mixes can only be done in the digital mixer, post

ADC conversion, or alternatively, other analog inputs can be connected for mixing.

The examples available are below - where [SE] is single ended, and [DIFF] is a differential input. Bold items are

the single channel selects.

Table 4. MUX, Mix and Polarity Input Selection

ADC1L and ADC2L

ADC1R and ADC2R

Code

0x00

No Selection (Mute)

0x01

VINL1[SE] (Default)

VINR1[SE] (Default)

0x02

VINL2[SE]

VINR2[SE]

0x03

VINL2[SE] + VINL1[SE]

VINR2[SE] + VINR1[SE]

0x04

VINL3[SE]

VINR3[SE]

0x05

VINL3[SE] + VINL1[SE]

VINR3[SE] + VINR1[SE]

0x06

VINL3[SE] + VINL2[SE]

VINR3[SE] + VINR2[SE]

0x07

VINL3[SE] + VINL2[SE] + VINL1[SE]

VINR3[SE] + VINR2[SE] + VINR1[SE]

0x08

VINL4[SE]

VINR4[SE]

0x09

VINL4[SE] + VINL1[SE]

VINR4[SE] + VINR1[SE]

0x0A

VINL4[SE] + VINL2[SE]

VINR4[SE] + VINR2[SE]

0x0B

VINL4[SE] + VINL2[SE] + VINL1[SE]

VINR4[SE] + VINR2[SE] + VINR1[SE]

0x0C

VINL4[SE] + VINL3[SE]

VINR4[SE] + VINR3[SE]

0x0D

VINL4[SE] + VINL3[SE] + VINL1[SE]

VINR4[SE] + VINR3[SE] + VINR1[SE]

0x0E

VINL4[SE] + VINL3[SE] + VINL2[SE]

VINR4[SE] + VINR3[SE] + VINR2[SE]

0x0F

VINL4[SE] + VINL3[SE] + VINL2[SE] + VINL1[SE]

VINR4[SE] + VINR3[SE] + VINR2[SE] + VINR1[SE]

0x10

{VIN1P, VIN1M}[DIFF]

{VIN2P, VIN2M}[DIFF]

0x20

{VIN4P, VIN4M}[DIFF]

{VIN3P, VIN3M}[DIFF]

0x30

{VIN1P, VIN1M}[DIFF] + {VIN4P, VIN4M}[DIFF]

{VIN2P, VIN2M}[DIFF] + {VIN3P, VIN3M}[DIFF]

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