PIC16F870SLASHP datasheet(40/156 Pages) MICROCHIP

40 / 156 page

PIC16F870/871

DS30569A-page 40

Preliminary

EECON1 REGISTER (ADDRESS 18Ch)

R/W-x

U-0

R/W-x

R/W-0

EEPGD

—

WRERR

WREN

R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n= Value at POR reset

bit7

bit0

bit 7:

EEPGD: Program / Data EEPROM Select bit

= Accesses Program memory

= Accesses data memory

(This bit cannot be changed while a read or write operation is in progress)

bit 6-4:

Unimplemented: Read as '0'

bit 3:

WRERR: EEPROM Error Flag bit

= A write operation is prematurely terminated

(any MCLR reset or any WDT reset during normal operation)

= The write operation completed

bit 2:

WREN: EEPROM Write Enable bit

= Allows write cycles

= Inhibits write to the EEPROM

bit 1:

WR: Write Control bit

= Initiates a write cycle. (The bit is cleared by hardware once write is complete.) The WR bit can only

be set (not cleared) in software.

= Write cycle to the EEPROM is complete

bit 0:

RD: Read Control bit

= Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not cleared) in

software.

= Does not initiate an EEPROM read

PIC16F870/P Datasheet(PDF) 40 Page - Microchip Technology

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