PIC16F870SLASHP datasheet(20/156 Pages) MICROCHIP

20 / 156 page

PIC16F870/871

DS30569A-page 20

Preliminary

2.2.2.5

PIR1 REGISTER

The PIR1 Register contains the individual flag bits for

the peripheral interrupts.

PIR1 REGISTER (ADDRESS 0Ch)

Note:

Interrupt flag bits get set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt bits are clear prior to enabling an

interrupt.

R/W-0

R-0

U-0

R/W-0

PSPIF(1)

ADIF

RCIF

TXIF



CCP1IF

TMR2IF TMR1IF

R = Readable bit

W = Writable bit

- n= Value at POR reset

bit7

bit0

bit 7:

PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit

= A read or a write operation has taken place (must be cleared in software)

= No read or write has occurred

bit 6:

ADIF: A/D Converter Interrupt Flag bit

= An A/D conversion completed

= The A/D conversion is not complete

bit 5:

RCIF: USART Receive Interrupt Flag bit

= The USART receive buffer is full

= The USART receive buffer is empty

bit 4:

TXIF: USART Transmit Interrupt Flag bit

= The USART transmit buffer is empty

= The USART transmit buffer is full

bit 7:

Unimplemented: Read as ‘0’

bit 2:

CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

= A TMR1 register capture occurred (must be cleared in software)

= No TMR1 register capture occurred

Compare Mode

= A TMR1 register compare match occurred (must be cleared in software)

= No TMR1 register compare match occurred

PWM Mode

Unused in this mode

bit 1:

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

= TMR2 to PR2 match occurred (must be cleared in software)

= No TMR2 to PR2 match occurred

bit 0:

TMR1IF: TMR1 Overflow Interrupt Flag bit

= TMR1 register overflowed (must be cleared in software)

= TMR1 register did not overflow

Note 1: PSPIF is reserved on the PIC16F870; always maintain this bit clear.

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