PIC16F870SLASHP datasheet(59/156 Pages) MICROCHIP

59 / 156 page

Preliminary

DS30569A -page 59

PIC16F870/871

8.2

Compare Mode

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the RC2/CCP1 pin is:

• Driven high

•Driven low

• Remains unchanged

The action on the pin is based on the value of control

bits CCP1M<3:0> (CCP1CON<3:0>). At the same

time, interrupt flag bit CCP1IF is set.

FIGURE 8-2:

COMPARE MODE OPERATION

BLOCK DIAGRAM

8.2.1

CCP PIN CONFIGURATION

The user must configure the RC2/CCP1 pin as an out-

put by clearing the TRISC<2> bit.

8.2.2

TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

8.2.3

SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen, the

CCP1 pin is not affected. The CCPIF bit is set causing

a CCP interrupt (if enabled).

8.2.4

SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated,

which may be used to initiate an action.

The special event trigger output of CCP1 resets the

TMR1 register pair and starts an A/D conversion (if the

A/D module is enabled). This allows the CCPR1 regis-

ter to effectively be a 16-bit programmable period reg-

ister for Timer1.

8.3

PWM Mode (PWM)

In pulse width modulation mode, the CCP1 pin pro-

duces up to a 10-bit resolution PWM output. Since the

CCP1 pin is multiplexed with the PORTC data latch, the

TRISC<2> bit must be cleared to make the CCP1 pin

an output.

Figure 8-3 shows a simplified block diagram of the CCP

module in PWM mode.

For a step-by-step procedure on how to set up the CCP

module for PWM operation, see Section 8.3.3.

FIGURE 8-3:

SIMPLIFIED PWM BLOCK

DIAGRAM

Note:

Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to the

default low level. This is not the data latch.

CCPR1H CCPR1L

TMR1H

TMR1L

Comparator

Output

Logic

Special Event Trigger

Set flag bit CCP1IF

(PIR1<2>)

match

RC2/CCP1

TRISC<2>

CCP1CON<3:0>

Mode Select

Output Enable

Special event trigger will:

reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),

and set bit GO/DONE (ADCON0<2>).

Note:

The special event trigger from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

Note:

Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default

low level. This is not the PORTC I/O data

latch.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(Note 1)

Duty Cycle Registers

CCP1CON<5:4>

Clear Timer,

CCP1 pin and

latch D.C.

TRISC<2>

RC2/CCP1

Note 1: 8-bit timer is concatenated with 2-bit internal Q clock

or 2 bits of the prescaler to create 10-bit time-base.

PIC16F870/P Datasheet(PDF) 59 Page - Microchip Technology

PIC16F870/P Datasheet(HTML) 59 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL