PIC16C641-04SLASHTQ datasheet(25/136 Pages) MICROCHIP

25 / 136 page

Preliminary

DS30559A-page 25

PIC16C64X & PIC16C66X

4.2.2.5

PIR1 REGISTER

This register contains the individual ﬂag bits for the

comparator and Parallel Slave Port interrupts.

Note:

Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable

bit,

GIE

(INTCON<7>).

User

software should ensure the appropriate

interrupt ﬂag bits are clear prior to enabling

an interrupt.

FIGURE 4-9:

PIR1 REGISTER (ADDRESS 0Ch)

R/W-0

U-0

PSPIF(1)

CMIF

—

R= Readable bit

W= Writable bit

U= Unimplemented bit,

read as ‘0’

- n= Value at POR reset

bit7

bit0

bit 7:

PSPIF(1): Parallel Slave Port Interrupt Flag bit

1 = A read or write operation has taken place (must be cleared in software)

0 = No read or write operation has taken place

bit 6:

CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed (must be cleared in software)

0 = Comparator input has not changed

bit 5-0: Unimplemented: Read as '0'

Note 1: Bit PSPIF is reserved on the PIC16C641/642, always maintain this bit clear.

PIC16C641-04/TQ Datasheet(PDF) 25 Page - Microchip Technology

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