PIC16C641-04SLASHTQ datasheet(66/136 Pages) MICROCHIP

66 / 136 page

PIC16C64X & PIC16C66X

DS30559A-page 66

Preliminary

9.5

Interrupts

The PIC16C641 and PIC16C642 have four sources of

interrupt, while the PIC16C661 and PIC16C662 have

five sources:

• External interrupt RB0/INT

• TMR0 overﬂow interrupt

• PORTB change interrupts (pins RB7:RB4)

• Comparator interrupt

• Parallel Slave Port interrupt (PIC16C661/662)

The interrupt control register, (INTCON), records

individual core interrupt requests in ﬂag bits. It also has

various individual enable bits and the global interrupt

enable bit.

The global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in

INTCON register. GIE is cleared on reset.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine as well as sets the GIE bit, which

allows any pending interrupt to execute.

Those interrupts associated with the “core” have their

ﬂag and enable bits in the INTCON register. The core

interrupts are: RB0/INT pin interrupt, the RB port

change interrupt, and the TMR0 overﬂow interrupt. The

INTCON register also contains the Peripheral Interrupt

Enable bit, PEIE. Bit PEIE will enable/mask the periph-

eral interrupts (CM and PSP) from vectoring when bit

PEIE is set/cleared.

Flag bits PSPIF and CMIF are contained in special

function register PIR1. The corresponding interrupt

enable bits (PSPIE and CMIE) are contained in special

function register PIE1.

When an interrupt is responded to, the GIE is cleared

to disable any further interrupt, the return address is

pushed into the stack and the PC is loaded with 0004h.

Once in the interrupt service routine the source(s) of

the interrupt can be determined by polling the interrupt

ﬂag bits. The interrupt ﬂag bit(s) must be cleared in

software before re-enabling interrupts to avoid recur-

sive interrupts.

For external interrupt events, such as the RB0/INT or

Port RB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs (Figure 9-16).

The latency is the same for one or two cycle

instructions. Once in the interrupt service routine the

source(s) of the interrupt can be determined by polling

the interrupt ﬂag bits. The interrupt ﬂag bit(s) must be

cleared in software before re-enabling interrupts to

avoid multiple interrupt requests. Individual interrupt

ﬂag bits are set regardless of the status of their

corresponding mask bit or the GIE bit.

Note 1: Individual interrupt ﬂag bits are set regard-

less of the status of their corresponding

mask bit or the GIE bit.

Note 2: When an instruction that clears the GIE bit

is executed, any interrupts that were

pending for execution in the next cycle are

ignored. The CPU will execute a NOP in

the

cycle

immediately

following

the

instruction which clears the GIE bit. The

interrupts which were ignored are still

pending to be serviced when the GIE bit is

set again.

FIGURE 9-15: INTERRUPT LOGIC

RBIF

RBIE

T0IF

T0IE

INTF

INTE

GIE

CMIE

Wake-up

(If in SLEEP mode)

Interrupt

CMIF

to CPU

PSPIE(1)

PSPIF(1)

PEIE

Note 1: The Parallel Slave Port is implemented on the PIC16C661 and PIC16C662 only.

PIC16C641-04/TQ Datasheet(PDF) 66 Page - Microchip Technology

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