ASX340AT datasheet(56/75 Pages) ONSEMI

56 / 75 page

ASX340AT/D Rev. H, 8/15 EN

©Semiconductor Components Industries, LLC, 2015.

ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Modes and Timing

I/O Timing

Digital Output

By default, the ASX340AT launches pixel data, FV, and LV synchronously with the falling

edge of PIXCLK. The expectation is that the user captures data, FV, and LV using the

rising edge of PIXCLK. The timing diagram is shown in Figure 36.

As an option, the polarity of the PIXCLK can be inverted from the default by program-

ming R0x0016[14].

Figure 36:

Digital Output I/O Timing

Note:

PIXCLK can be inverted from the default by programming R0x0016[14].

Table 29:

Parallel Digital Output I/O Timing

fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;

VDD_PLL = 2.8V; VDD_DAC = 2.8V; Default slew rate

Signal

Parameter

Conditions

Min

Typ

Max

Unit

EXTCLK

fextclk

MHz

textclk_period

18.52

166.67

Duty cycle

PIXCLK1

fpixclk

MHz

tpixclk_period

18.52

37.04

166.67

Duty cycle

DATA[7:0]

tpixclkf_dout

1.55

–

1.9

tdout_su

–

tdout_ho

–

FV/LV

tpixclkf_fvlv

1.6

–

3.05

tfvlv_su

–

tfvlv_ho

–

EXT CLK

PIXC LK

D OUT [7:0]

F R AM E_VALID

LIN E _VALID

pixclkf_dout

pixclkf_fvlv

Input

O utput

fvlv_su

fvlv_ho

dout_ho

dout_su

extclk_period

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