ASX340AT datasheet(40/75 Pages) ONSEMI

40 / 75 page

ASX340AT/D Rev. H, 8/15 EN

©Semiconductor Components Industries, LLC, 2015.

ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Slave Two-Wire Serial Interface

Sequential READ, Start from Random Location

This sequence (Figure 19) starts in the same way as the single READ from random loca-

tion (Figure 17 on page 39). Instead of generating a no-acknowledge bit after the first

byte of data has been transferred, the master generates an acknowledge bit and

continues to perform byte READs until “L” bytes have been read.

Figure 19:

Sequential READ, Start from Random Location

Sequential READ, Start from Current Location

This sequence (Figure 20) starts in the same way as the single READ from current loca-

tion (Figure 18). Instead of generating a no-acknowledge bit after the first byte of data

has been transferred, the master generates an acknowledge bit and continues to

perform byte reads until “L” bytes have been read.

Figure 20:

Sequential READ, Start from Current Location

Single Write to Random Location

Figure 21 shows the typical WRITE cycle from the host to the ASX340AT.The first 2 bytes

indicate a 16-bit address of the internal registers with most-significant byte first. The

following 2 bytes indicate the 16-bit data.

Figure 21:

Single WRITE to Random Location

Read Data

(15:8)

Read Data

(15:8)

Read Data

(7:0)

Slave Address

A Reg Address[15:8]

Reg Address[7:0]

Read Data

Slave Address

Previous Reg Address, N

Reg Address, M

M+1

M+2

M+1

M+3

M+L-2

M+L-1

M+L

Read Data

(15:8)

Read Data

(7:0)

Read Data

(15:8)

Read Data

(7:0)

Read Data

(7:0)

Read Data

Previous Reg Address, N

N+1

N+2

N+L-1

N+L

Read Data

Slave Address

Read Data

(15:8)

Read Data

(7:0)

Read Data

(15:8)

Read Data

(7:0)

Read Data

(15:8)

Read Data

(7:0)

Read Data

(15:8)

Read Data

(7:0)

Slave Address

A Reg Address[15:8]

Reg Address[7:0]

Previous Reg Address, N

Reg Address, M

M+1

Write Data

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