LM5027ASQSLASHNOPB datasheet(4/35 Pages) TI

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LM5027A

SNVS642B – APRIL 2010 – REVISED MARCH 2013

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Table 1. Pin Descriptions (continued)

Pin(1)

Name

Description

Application Information

OUTB

Output driver

Control output of the active clamp PFET gate. Capable of 1A peak source and

sink current.

OUTA

Output driver

Control output of the main PWM NFET gate. Capable of 2A peak source and sink

current.

OUTSR

Output driver

Control output of the secondary side synchronous rectifier FET gates. Capable of

3A peak source and sink current.

PGND

Power ground

Connect directly to Analog Ground

VCC

Start-up regulator output

Output of the internal high voltage start-up regulator. Regulated at 9.5V during

start-up and 7.5V during run mode. If the auxiliary winding raises the voltage on

this pin above the regulation set point, the internal start-up regulator will

shutdown, thus reducing the IC power dissipation.

Current sense input

Current sense input for cycle-by-cycle current limiting. If the CS pin exceeds

500mV the output pulse will be terminated, entering cycle-by-cycle current limit.

An internal switch holds CS low for 100 ns after OUTA switches high to blank

leading edge transients.

Soft-start Input

An internal 22 µA current source charges an external capacitor to set the soft-start

rate.

RES

Restart timer

If cycle-by-cycle current limit is reached during any cycle, a 22 µA current is

sourced into the RES capacitor. If the RES capacitor voltage charges to 1.0V, a

hiccup sequence is initiated. The SS and SSSR capacitors are discharged and the

control outputs are disabled. The voltage on the RES capacitor is ramped

between 4V and 2V eight times. After the eighth cycle, the SS capacitor is

released and the normal start-up sequence begins.

SSSR

Soft-start for synchronous

An external capacitor and an internal 25 µA current source sets the soft-start and

rectifier output.

soft-stop ramps for the synchronous rectifier output (OUTSR).

OTP

Over-Temperature

The OTP comparator can be used for over-temperature shutdown protection with

Protection

an external NTC thermistor voltage divider setting the shutdown temperature. The

OTP comparator threshold is 1.25V. Hysteresis is set by an internal current

source that sources 20 µA into the external resistor divider when the OTP pin

voltage is above the threshold.

UVLO

Line under-voltage lockout

An external voltage divider from the power source sets the shutdown and standby

comparator levels. When UVLO reaches the 0.4V threshold, the VCC and REF

regulators are enabled. When UVLO reaches the 2.0V threshold, the SS pin is

released and the device enters the active mode. Hysteresis is set by an internal

current source that pulls 20 µA from the external resistor divider when the UVLO

pin is below the 2.0V threshold.

Exposed pad, underside of

No electrical contact to the LM5027A integrated circuit. Connect to system ground

package

plane for reduced thermal resistance.

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