LAN9730 datasheet(19/222 Pages) MICROCHIP

19 / 222 page

 2012-2015 Microchip Technology Inc.

DS00001946A-page 19

LAN9730/LAN9730i

TABLE 2-3:

JTAG PINS

Num Pins

Name

Symbol

Buffer

Type

Description

1JTAG Test

Port Reset

(Internal PHY

Mode)

nTRST

(PU)

In Internal PHY Mode, this active-low pin func-

tions as the JTAG test port reset input.

Receive Data

(External

PHY Mode)

RXD0

(PD)

In External PHY Mode, this pin functions as the

receive data 0 input from the external PHY.

1JTAG Test

Data Out

(Internal PHY

Mode)

TDO

In Internal PHY Mode, this pin functions as the

JTAG data output.

PHY Reset

(External

PHY Mode)

nPHY_RST

In External PHY Mode, this active-low pin func-

tions as the PHY reset output.

1JTAG Test

Clock

(Internal PHY

Mode)

TCK

(PU)

In Internal PHY Mode, this pin functions as the

JTAG test clock. The maximum operating fre-

quency of this clock is 25 MHz.

Receive Data

(External

PHY Mode)

RXD1

(PD)

In External PHY Mode, this pin functions as the

receive data 1 input from the external PHY.

1JTAG Test

Mode Select

(Internal PHY

Mode)

TMS

(PU)

In Internal PHY Mode, this pin functions as the

JTAG test mode select.

Receive Data

(External

PHY Mode)

RXD2

(PD)

In External PHY Mode, this pin functions as the

receive data 2 input from the external PHY.

1JTAG Test

Data Input

(Internal PHY

Mode)

TDI

(PU)

In Internal PHY Mode, this pin functions as the

JTAG data input.

Receive Data

(External

PHY Mode)

RXD3

(PD)

In External PHY Mode, this pin functions as the

receive data 3 input from the external PHY.

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