L6751B datasheet(33/58 Pages) STMICROELECTRONICS

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L6751B

Output voltage positioning

Doc ID 024028 Rev 1

33/58

6.7.1

LSLESS startup and pre-bias output

Any time the device resumes from an “OFF” code and at the first power-up, in order to avoid

any kind of negative undershoot on the load side, the L6751B performs a special sequence

in enabling the drivers: during the soft-start phase, the LS driver results as being disabled

(LS=OFF - PWMx set to HiZ and ENDRV = 0) until the first PWM pulse. After the first PWM

pulse, PWMx outputs switch between logic “0” and logic “1” and ENDRV is set to logic “1”.

This particular sequence avoids the dangerous negative spike on the output voltage that

can occur if starting over a pre-biased output.

Low-side MOSFET turn-on is masked only from the control loop point of view: protection is

still allowed to turn on the low-side MOSFET if overvoltage is needed.

6.8

DVID optimization: REF/SREF

High slew rate for dynamic VID transitions causes undershoot on the regulated voltage,

causing violation in the microprocessor requirement. To compensate this behavior and to

remove any undershoot in the transition, each section features DVID optimization circuit.

The reference used for the regulation is available on the REF/SREF pin (see Figure 10).

Connect an RREF/CREF to GND (RSREF/CSREF for the single-phase) to optimize the DVID

behavior. Components may be designed as follows (multi-phase, same equations apply to

single-phase):

Equation 9

where

ΔVosc is the PWM ramp and kV the gain for the voltage loop (see Section 11).

During a falling DVID transition, the REF pin moves according to the DVID command issued;

the current requested to charge/discharge the RREF/CREF network is mirrored and added to

the droop current compensating for undershoot on the regulated voltage.

Figure 8.

SLESS startup: enabled (left) Figure 9.

LSLESS startup: disabled

(right)

AM14840v1

AM14841v1

REF

ΔV

OSC

⋅

----------------------

–

⎝⎠

⎛⎞

⋅

REF

⋅

REF

----------------------

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