L6751B datasheet(43/58 Pages) STMICROELECTRONICS

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L6751B

Efficiency optimization

Doc ID 024028 Rev 1

43/58

9.2.1

VFDE and DrMOS

To guarantee correct behavior for DrMOS power stage compliant with Intel specification

rev3, it is recommended to control the DrMOS’ SMOD input through the ENDRV/SENDRV

pins of the L6751B. DrMOS enable must be controlled with the same signal used for the

L6751B EN pin.

Proper HiZ level can be programmed by adding proper external resistor divider across

PWM1 and PWM2. See Section 4.2 for details about HiZ level recognition. See reference

schematic in Figure 1.

9.3

Gate drive control (GDC)

Gate drive control (GDC) is a proprietary function which allows the L6751B to dynamically

control the Power MOSFET driving voltage in order to further optimize the overall system

efficiency. According to the SVI power state commanded and the configuration received

through the PMBus, the device switches this pin (GDC) between VCC5 or VDRV (inputs).

By connecting the power supply of external drivers directly to this pin, it is then possible to

carefully control the external MOSFET driving voltage.

In fact, high driving voltages are required to obtain good efficiency in high loading

conditions. On the contrary, in lower loading conditions, such high driving voltage penalizes

efficiency because of high losses in Qgs. GDC allows to tune the MOSFET driving voltage

according to the delivered current.

The default configuration considers GDC always switched to VDRV except when entering

power states higher than PS01h (included): in this case, to further increase efficiency,

simply supply Phase1 and Phase2 driver through the GDC pin. Their driving voltage is

automatically updated as lower power states are commanded through the SVI interface.

Further optimization may be possible by properly setting an automatic GDC threshold

through the dedicated PMBus command and/or pinstrapping. It is then possible to enable

the gate driving voltage switchover even in PS00h. According to the positioning of the

threshold compared with DPM thresholds, it is possible to achieve different performances.

Simulations and/or bench tests may be of help in defining the best performing configuration

achievable with the active and passive components available.

Figure 12.

Output current vs. switching frequency in PSK mode

Iout = Ipp/2

Iout < Ipp/2

Tsw

Tvfde

AM14844v1

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