MSP430FR6972IPM datasheet(6/157 Pages) TI1

6 / 157 page

MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872

MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

SLASE23C – JANUARY 2015 – REVISED MAY 2015

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Device Comparison

Table 3-1 and Table 3-2 summarize the available family members.

Table 3-1. Device Comparison – Family Members With UART BSL

eUSCI

FRAM

SRAM

CLOCK

PACKAGE

DEVICE

Timer_A(1)

Timer_B(2)

AES

ADC12_B

LCD_C

I/O

(KB)

SYSTEM

TYPE

A(3)

B(4)

DCO

3, 3(5)

64 PM

MSP430FR6972

HFXT

yes

8 ext

112 seg

2, 5 (6)(7)

64 RGC

LFXT

DCO

3, 3(5)

64 PM

MSP430FR6872

HFXT

8 ext

112 seg

2, 5 (6)(7)

64 RGC

LFXT

DCO

3, 3(5)

64 PM

MSP430FR6970

HFXT

yes

8 ext

112 seg

2, 5 (6)(7)

64 RGC

LFXT

DCO

3, 3(5)

64 PM

MSP430FR6870

HFXT

8 ext

112 seg

2, 5 (6)(7)

64 RGC

LFXT

116 seg

64 PM

DCO

3, 3(5)

MSP430FR6922

yes

8 ext

100 seg

64 RGC

LFXT

2, 5 (6)(7)

46 (DGG)

(DGG)

56 DGG

116 seg

64 PM

DCO

3, 3(5)

MSP430FR6822

8 ext

100 seg

64 RGC

LFXT

2, 5 (6)(7)

46 (DGG)

(DGG)

56 DGG

116 seg

64 PM

DCO

3, 3(5)

MSP430FR6920

yes

8 ext

100 seg

64 RGC

LFXT

2, 5 (6)(7)

46 (DGG)

(DGG)

56 DGG

116 seg

64 PM

DCO

3, 3(5)

MSP430FR6820

8 ext

100 seg

64 RGC

LFXT

2, 5 (6)(7)

46 (DGG)

(DGG)

56 DGG

(1)

Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a

number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output

generators, respectively.

(2)

Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a

number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output

generators, respectively.

(3)

eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.

(4)

eUSCI_B supports I2C with multiple slave addresses and SPI.

(5)

Timer_A TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.

(6)

Timer_A TA2 provides only internal capture/compare inputs and only internal PWM outputs (if any).

(7)

Timer_A TA3 provides only internal capture/compare inputs and only internal PWM outputs (if any) for FR692x(1) and FR682x(1) with RGC and PM packages. For FR692x(1) and

FR682x(1) with DGG package and all other devices, Timer_A TA3 provides internal, external capture/compare inputs and internal, external PWM outputs (if any).

Device Comparison

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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721

MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

MSP430FR6972IPM Datasheet(PDF) 6 Page - Texas Instruments

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