TS32101

Final Datasheet

Rev 2.1

January 26, 2016

www.semtech.com

10 of 12

Semtech

Functional Description (continued)

Packaging Information

Pb-Free (RoHS):TheTS32101devicesarefullycompliantforallmaterialscoveredbyEuropeanUnionDirective2002/95/EC,and

meetallIPC-1752Level3materialsdeclarationrequirements.

MSL, Peak Temp:TheTS32101familyhasaMoistureSensitivityLevel(MSL)1ratingperJEDECJ-STD-020D.Thesedevicesalso

haveaPeakProfileSolderTemperature(Tp)of260°C.

Ordering Information

TS32101-QFNR

Application Using A Multi-Layer PCB

Tomaximizetheefficiencyofthispackageforapplicationonasinglelayerormulti-layerPCB,certainguidelinesmustbefollowed

whenlayingoutthispartonthePCB.

The following are guidelines for mounting the exposed pad IC on a Multi-Layer PCB with ground a plane.

Package Thermal Pad

Solder Pad (Land Pattern)

Thermal Via's

Package Outline

Package and PCB Land Configuration

For a Multi-Layer PCB

JEDEC standard FR4 PCB Cross-section:

(square)

Package Solder Pad

Package Solder Pad

(bottom trace)

Thermal Via

Component Traces

Thermal Isolation

Power plane only

1.5748mm

0.0 - 0.071 mm Board Base

& Bottom Pad

0.5246 - 0.5606 mm

Power Plane

(1oz Cu)

1.0142 - 1.0502 mm

Ground Plane

(1oz Cu)

1.5038 - 1.5748 mm

Component Trace

(2oz Cu)

2 Plane

4 Plane

Multi-Layer Board (Cross-sectional View)