DSD1796DBRG4 datasheet(16/61 Pages) TI1

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DSD1796

SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006

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AUDIO DATA INTERFACE

Audio Serial Interface

The audio interface port is a 3-wire serial port. It includes PLRCK (pin 4), PBCK (pin 6), and PDATA (pin 5). PBCK is the

serial audio bit clock, and it is used to clock the serial data present on PDATA into the serial shift register of the audio

interface. Serial data is clocked into the DSD1796 on the rising edge of PBCK. PLRCK is the serial audio left/right word

clock.

The DSD1796 requires the synchronization of PLRCK and the system clock, but does not need a specific phase relation

between PLRCK and the system clock.

If the relationship between PLRCK and the system clock changes more than

±6 PBCK, internal operation is initialized within

1/fS and analog outputs are forced to the bipolar zero level until resynchronization between PLRCK and the system clock

is completed.

PCM Audio Data Formats and Timing

The DSD1796 supports industry-standard audio data formats, including standard right-justified, I2S, and left-justified. The

data formats are shown in Figure 27. Data formats are selected using the format bits, FMT[2:0], in control register 18. The

default data format is 24-bit I2S. All formats require binary 2s complement, MSB-first audio data. Figure 26 shows a detailed

timing diagram for the serial audio interface.

PDATA

t(BCH)

1.4 V

PBCK

PLRCK

t(BCL)

t(LB)

t(BCY)

t(DS)

t(DH)

1.4 V

t(BL)

PARAMETERS

MIN

MAX

UNITS

t(BCY)

PBCK pulse cycle time

t(BCL)

PBCK pulse duration, LOW

t(BCH)

PBCK pulse duration, HIGH

t(BL)

PBCK rising edge to PLRCK edge

t(LB)

PLRCK edge to PBCK rising edge

t(DS)

PDATA setup time

t(DH)

PDATA hold time

—

PLRCK clock data

50%

± 2 bit clocks

Figure 26. Timing of Audio Interface

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