DP8430V datasheet(24/56 Pages) NSC

24 / 56 page

50 Refresh Options (Continued)

523 Error Scrubbing during Refresh

The DP8430V31V32V support error scrubbing during all

RAS DRAM refreshes Error scrubbing during refresh is se-

lected through bits C4 – C6 with bit R9 negated during pro-

gramming Error scrubbing can not be used with staggered

refresh (see Section 80) Error scrubbing during refresh al-

lows a CAS or group of CASs to assert during the all RAS

refresh as shown in

Figure 18 This allows data to be read

from the DRAM array and passed through an Error Detec-

tion And Correction Chip EDAC If the EDAC determines

that the data contains a single bit error and corrects that

error the refresh cycle can be extended with the input ex-

tend refresh EXTNDRF and a read-modify-write operation

can be performed by asserting WE It is the responsibility of

the designer to ensure that WE is negated The DP8432V

has a 24-bit internal refresh address counter that contains

the 11 row

11 column and 2 bank addresses

The

DP8430V31V have a 22-bit internal refresh address coun-

ter that contains the 10 row 10 column and 2 bank address-

es These counters are configured as bank column row

with the row address as the least significant bits The bank

counter bits are then used with the programming selection

to determine which CAS or group of CASs will assert during

a refresh

TLF11118 – 27

FIGURE 18 Error Scrubbing during Refresh (Two Refresh Cycles Shown)

DP8430V Datasheet(PDF) 24 Page - National Semiconductor (TI)