DP8430V datasheet(20/56 Pages) NSC

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50 Refresh Options

The DP8430V31V32V support two refresh control mode

options

1 Automatic Internally Controlled Refresh

2 Externally Controlled Refresh

With each of the control modes above three types of re-

fresh can be performed

1 All RAS Refresh

2 Staggered Refresh

3 Error Scrubbing During All RAS Refresh

There are two inputs EXTNDRF and RFSH and two out-

puts RFIP and RFRQ associated with refresh There are

also ten programming bits R0 – 1 R9 C0 – 6 and ECAS0

used to program the various types of refreshing

Asserting the input EXTNDRF extends the refresh cycle for

a single or multiple integral periods of CLK

The output RFIP is asserted one period of CLK before the

first refresh RAS is asserted If an access is currently in

progress RFIP will be asserted up to one period of CLK

before the first refresh RAS after AREQ or AREQB is nega-

ted for the access (see

Figure 13 )

The DP8430V31V32V will increment the refresh address

counter automatically independent of the refresh mode

used The refresh address counter will be incremented once

all the refresh RASs have been negated

In every combination of refresh control mode and refresh

type the DP8430V31V32V is programmed to keep RAS

asserted a number of CLK periods The time values of RAS

low during refresh are programmed through programming

bits R0 and R1

51 REFRESH CONTROL MODES

511 Automatic Internal Refresh

To select Automatic Internal Refresh the user must choose

ECAS0 e 0 during programming The DP8430V31V32V

have an internal refresh clock The period of the refresh

clock is generated from the programming bits C0 – 3 Every

period of the refresh clock an internal refresh request is

generated As long as a DRAM access is not currently in

progress and precharge time has been met the internal re-

fresh request will generate an automatic internal refresh If a

DRAM access is in progress the DP8430V31V32V on-

chip arbitration logic will wait until the access is finished

before performing the refresh The refreshaccess arbitra-

tion logic can insert a refresh cycle between two address

pipelined accesses However the refresh arbitration logic

can not interrupt an access cycle to perform a refresh

TLF11118 – 20

Explanation of Terms

RFRQ e ReFresh ReQuest internal to the DP8430V31V32V RFRQ has the ability to hold off a pending access

RFSH e Externally requested ReFreSH

RFIP e

ReFresh in Progress

ACIP e

Port A or Port B (DP8432V only) ACcess in Progress This means that either RAS is low for an access or is in the process of

transitioning low for an access

FIGURE 13 DP8430V31V32V AccessRefresh Arbitration State Program

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