DP8430V datasheet(36/56 Pages) NSC

Part #	DP8430V

Description	microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers

PDF	56 Pages

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Manufacturer	NSC [National Semiconductor (TI)]

Direct Link	http://www.national.com

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36 / 56 page

100 Dual Accessing (DP8432V) (Continued)

Since the DP8432V has only one set of address inputs the

signal is used with the addition of buffers to allow the cur-

rently granted port’s addresses to reach the DP8432V The

signals which need to be bufferred are R0 – 10 C0 – 10

B0 – 1 ECAS0–3 WE and LOCK All other inputs are not

common and do not have to be buffered as shown in

Figure

32a If a Port which is not currently granted tries to access

the DRAM array the GRANTB output will transition from a

rising clock edge from AREQ or AREQB negating and will

precede the RAS for the access by one or two clock peri-

ods GRANTB will then stay in this state until the other port

requests an access and the currently granted port is not

accessing the DRAM as shown in

Figure 32b

TLF11118 – 53

If Port B is synchronous the Request Synchronizing logic will not be required

FIGURE 32a Dual Accessing with the DP8432V (System Block Diagram)

DP8430V Datasheet(PDF) 36 Page - National Semiconductor (TI)