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TAS3108DCPR Datasheet(PDF) 22 Page - Texas Instruments |
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TAS3108DCPR Datasheet(HTML) 22 Page - Texas Instruments |
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22 / 63 page  www.ti.com SCLKIN OSC PLL and Clock Management 2xSDA Audio DSP Core MCLKO PLL1 PLL0 SCLKOUT1 LRCLK MICROCLK_DIV SCLKOUT2 2xSCL 8-Bit WARP 8051 Microprocessor 1/2N 1/(M+1) I2C Master/Slave Controller ÷10 Master SCL MCLKI XTALI XTALO M U X ÷Y = 64DEFAULT M U X M U X ÷2 ÷2 M U X MCLK PLL × 11 M U X ÷2 ÷2 M U X ÷4 M U X Input SAP Microprocessor and I2C Bus Controller Output SAP N = 0 (Default) ÷ X = 1DEFAULT Oversample Clock B0078-01 ÷ Z = 2DEFAULT PLL2 M = 8 (Default) TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 Figure 5-2. DPLL and Clock Management Block Diagram Clock Controls 22 Submit Documentation Feedback Not Recommended for New Designs |
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