TAS3108DCPR datasheet(47/63 Pages) TI1

47 / 63 page

www.ti.com

8.5.2

Serial Audio Port Slave Mode Signals (TAS3108/TAS3108IA)

th1

tsu1

tpd1

tpd2

tsu2

th2

tc(SCLKIN)

T0090-01

SCLKIN

LRCLK

(Input)

SDOUT1

SDOUT2

SDOUT3

SDOUT4

SCLKOUT2

SDIN1

SDIN2

SDIN3

SDIN4

tw(SCLKIN)

TAS3108, TAS3108IA

AUDIO DIGITAL SIGNAL PROCESSORS

SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST

MIN

TYP

MAX

UNIT

CONDITIONS

fLRCLK

Frequency, LRCLK (fS)

32(1)

192(1)

kHz

tw(SCLKIN) Pulse duration, SCLKIN high

See (2)

0.4 tc(SCLKIN)

(1)

0.5 tc(SCLKIN) 0.6 tc(SCLKIN)

(1)

fSCLKIN

Frequency, SCLKIN

See (3)

64 fS

(1)

25(1)

MHz

tpd1

Propagation delay, SCLKIN falling edge to SDOUT

15(1)

tsu1

Setup time, LRCLK to SCLKIN rising edge

10(1)

th1

Hold time, LRCLK from SCLKIN rising edge

0.5 tc(SCLKIN)

(1)

tsu2

Setup time, SDIN to SCLKIN rising edge

10(1)

th2

Hold time, SDIN from SCLKIN rising edge

10(1)

Propagation delay, SCLKIN falling edge to

tpd2

17(1)

SCLKOUT2 falling edge

(1)

This measurement is specified by design.

(2)

Period of SCLKIN = TSCLKIN = 1/fSCLKIN

(3)

Duty cycle is 50/50.

Figure 8-2. Serial Audio Port Slave Mode Timing Waveforms

Submit Documentation Feedback

Electrical Specifications

Not Recommended for New Designs

TAS3108DCPR Datasheet(PDF) 47 Page - Texas Instruments

TAS3108DCPR Datasheet(HTML) 47 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Datasheet Download

Link URL