LMV844MTSLASHNOPB datasheet(16/38 Pages) TI1

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ESD

D1 D2

ESD

VOUT

LMV841, LMV842, LMV844

LMV841-Q1, LMV842-Q1, LMV844-Q1

SNOSAT1H – OCTOBER 2006 – REVISED JULY 2016

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Product Folder Links: LMV841 LMV842 LMV844 LMV841-Q1 LMV842-Q1 LMV844-Q1

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Feature Description (continued)

Figure 34. Protection Diodes Between the Input Pins

7.3.2 Input Stage

The input stage of this amplifier consists of both a PMOS and an NMOS input pair to achieve a rail-to-rail input

range. For input voltages close to the negative rail, only the PMOS pair is active. Close to the positive rail, only

the NMOS pair is active. In a transition region that extends from approximately 2 V below V+ to 1 V below V+,

both pairs are active, and one pair gradually takes over from the other. In this transition region, the input-referred

offset voltage changes from the offset voltage associated with the PMOS pair to that of the NMOS pair. The input

pairs are trimmed independently to ensure an input offset voltage of less then 0.5 mV at room temperature over

the complete rail-to-rail input range. This also significantly improves the CMRR of the amplifier in the transition

region.

NOTE

The CMRR and PSRR limits in the tables are large-signal numbers that express the

maximum variation of the input offset of the amplifier over the full common-mode voltage

and supply voltage range, respectively. When the common-mode input voltage of the

amplifier is within the transition region, the small signal CMRR and PSRR may be slightly

lower than the large signal limits.

7.4 Device Functional Modes

7.4.1 Driving Capacitive Load

The LMV84x can be connected as noninverting unity gain amplifiers. This configuration is the most sensitive to

capacitive loading. The combination of a capacitive load placed on the output of an amplifier along with the

output impedance of the amplifier creates a phase lag, which reduces the phase margin of the amplifier. If the

phase margin is significantly reduced, the response is under-damped, which causes peaking in the transfer.

When there is too much peaking, the op amp might start oscillating.

The LMV84x can directly drive capacitive loads up to 100 pF without any stability issues. To drive heavier

capacitive loads, an isolation resistor (RISO) must be used, as shown in Figure 35. By using this isolation resistor,

the capacitive load is isolated from the output of the amplifier, and hence, the pole caused by CL is no longer in

the feedback loop. The larger the value of RISO, the more stable the output voltage is. If values of RISO are

sufficiently large, the feedback loop is stable, independent of the value of CL. However, larger values of RISO

result in reduced output swing and reduced output current drive.

LMV844MT/NOPB Datasheet(PDF) 16 Page - Texas Instruments