TMS320C6711 datasheet(83/129 Pages) TI

83 / 129 page

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088L − FEBRUARY 1999 − REVISED MAY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

SYNCHRONOUS DRAM TIMING

timing requirements for synchronous DRAM cycles† (see Figure 34) [C6711]

C6711-100

C6711-150

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

tsu(EDV-EKOH)

Setup time, read EDx valid before ECLKOUT high

2.5

th(EKOH-EDV)

Hold time, read EDx valid after ECLKOUT high

2.1

timing requirements for synchronous DRAM cycles† (see Figure 34) [C6711B]

NO.

C6711B-100

C6711BGFNA-100

C6711B-150

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

tsu(EDV-EKOH)

Setup time, read EDx valid before ECLKOUT high

2.5

th(EKOH-EDV)

Hold time, read EDx valid after ECLKOUT high

2.5

timing requirements for synchronous DRAM cycles† (see Figure 34) [C6711C/C6711D]

NO.

GDPA-167

−200

−250 (6711D)

UNIT

MIN

MAX

tsu(EDV-EKOH)

Setup time, read EDx valid before ECLKOUT high

1.5

th(EKOH-EDV)

Hold time, read EDx valid after ECLKOUT high

2.5

† The C6711/11B/11C/11D SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word

bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.

TMS320C6711 Datasheet(PDF) 83 Page - Texas Instruments

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