TMS320C6711 datasheet(20/129 Pages) TI

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TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088L − FEBRUARY 1999 − REVISED MAY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Table 15. Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12 [11D only], and CLKMODE0)†

CONFIGURATION

GFN and GDP

FUNCTIONAL DESCRIPTION

HD12

C15

EMIF Big Endian mode correctness (EMIFBE) [C6711D only]

0 – The EMIF data will always be presented on the ED[7:0] side of the bus, regardless of

the endianess mode (Little/Big Endian).

1 − In Little Endian mode (HD8 =1), the 8-bit or 16-bit EMIF data will be present on the

ED[7:0] side of the bus.

In Big Endian mode (HD8 =0), the 8-bit or 16-bit EMIF data will be present on the

ED[31:24] side of the bus [default].

This enhancement is not supported on the C6711/11B/11C device.

For proper C6711/11B/11C device operation, do not oppose the internal pullup (IPU) resistor

on this pin.

This new functionality does not affect systems using the current default value of HD12=1. For

more detailed information on the big endian mode correctness, see the EMIF Big Endian Mode

Correctness [C6711D Only]

portion of this data sheet.

HD8

B17

Device Endian mode (LEND)

0 – System operates in Big Endian mode

1 − System operates in Little Endian mode (default)

HD[4:3]

(BOOTMODE)

C19, C20

Bootmode Configuration Pins (BOOTMODE)

00 – CE1 width 32-bit, HPI boot/Emulation boot

01 – CE1 width 8-bit, Asynchronous external ROM boot with default

timings (default mode)

10 − CE1 width 16-bit, Asynchronous external ROM boot with default

timings

11 − CE1 width 32-bit, Asynchronous external ROM boot with default

timings

For more detailed information on these bootmode configurations, see the bootmode section of

this data sheet.

CLKMODE0

For the C6711 and C6711B devices, clock mode select

0 − Bypass mode (x1). CPU clock = CLKIN

1 − PLL mode (x4). CPU clock = 4 x CLKIN [default]

For the C6711C and C6711D devices, clock generator input clock source select

0 – Reserved. Do not use.

1 − CLKIN square wave [default]

For proper C6711C/C6711D device operation, this pin must be either left unconnected or

externally pulled up with a 1-kΩ resistor.

† All other HD pins [HD [15:9, 7:5, 2:0] (for 11/11B/11C) or HD [15:13, 11:9, 7:5, 2:0] (for 11D)] have pullups/pulldowns (IPUs or IPDs). For proper

device operation of the HD [15:9, 7, 1, 0] (for 11/11B/11C) or HD [14, 13, 11:9, 7, 1, 0] (for 11D), do not oppose these pins with external

pullups/pulldowns at reset; however, the HD[6, 5, 2] (for 11/11B/11C) or HD[15, 6, 5, 2] (for 11D) pins can be opposed and driven during reset.

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