TSB41AB3IPFPEP datasheet(39/55 Pages) TI1

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TSB41AB3EP

IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER

SGLS122C − JULY 2002 − REVISED JUNE 2008

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

receive (continued)

The sequence of events for a normal packet reception is as follows:1

Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL

lines. Normally, the interface is idle when receive is asserted. However, the receive operation may

interrupt a status transfer operation that is in progress so that the CTL lines may change from status

to receive without an intervening idle.

Data-on indication. The PHY may assert the data-on indication code on the D lines for one or more

cycles preceding the speed-code.

Speed code. The PHY indicates the speed of the received packet by asserting a speed code on the D

lines for one cycle immediately preceding packet data. The link decodes the speed code on the first

receive cycle for which the D lines are not the data-on code. If the speed code is invalid, or indicates

a speed higher that that which the link is capable of handling, the link should ignore the subsequent data.

Receive data. Following the data-on indication (if any) and the speed-code, the PHY asserts packet

data on the D lines with receive on the CTL lines for the remainder of the receive operation.

Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL

lines. The PHY asserts at least one cycle of idle following a receive operation.

(a)

(b)

(c)

FF (data-on)

D0–D7

CTL0, CTL1

SYSCLK

Figure 20. Null Packet Reception Timing

The sequence of events for a null packet reception is as follows:1

Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL

lines. Normally, the interface is idle when receive is asserted. However, the receive operation may

interrupt a status transfer operation that is in progress so that the CTL lines may change from status

to receive without an intervening idle.

Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles.

Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL

lines. The PHY asserts at least one cycle of idle following a receive operation.

Table 20. Receive Speed Codes

D0–D7

DATA RATE

00XX XXXX

S100

0100 XXXX

S200

0101 0000

S400

1YYY YYYY

data-on indication

NOTE: X = Output as 0 by PHY, ignored by LLC.

Y = Output as 1 by PHY, ignored by LLC.

TSB41AB3IPFPEP Datasheet(PDF) 39 Page - Texas Instruments

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