Datasheet

Datasheet

10/34

TSZ02201-0F1F0C100240-1-2

© 2013 ROHM Co., Ltd. All rights reserved.

15.Feb.2016 Rev.006

www.rohm.com

TSZ22111・15・001

BD9486F

○Pin 9: RT

This is the DC/DC switching frequency setting pin. DCDC frequency is decided

by connected resistor.

○

The relationship between the frequency and RT resistance value (ideal)

The oscillation setting ranges from 50kHz to 800kHz.

The setting example is separately described in the section ”3.2.5 DCDC

Oscillation Frequency Setting”

The fail logic indicating the abnormal state can be obtained by using the right

circuit example. The gate capacitor is limited to 200pF. We recommend

RE1C001VN for M1.The RT pin output the 2.0V(typ.) in the normal state and

drops to 0V in the latch off state. When REG50 reaches to 0V,there is a point

that FAIL output voltage is unstable, if this is a problem, please add C1 capacitor.

Please refer to section “2.7 Behavior List of the Protect Functions” or “3.5 Timing

Chart”.

○Pin 10: FB

This is the output terminal of error amplifier.

FB pin rises with the same slope as the SS pin during the soft-start period.

After soft -start completion (SS>3.7V), it operates as follows.

When PWM=H, it detects ISENSE terminal voltage and outputs error signal compared to analog dimming signal (ADIM).

It detects over boost (FBMAX) over FB=4.0V(typ). After the SS completion, if FB>4.0V and PWM=H continues 4clk GATE,

the CP charge starts. After that, only the FB>4.0V is monitored, if CP charge continues to the CP=3.0V, IC will be latched

off. (Please refer to section “3.5.6 Timing Chart”.)

The loop compensation setting is described in section "3.4 Loop Compensation".

○Pin 11: ISENSE

This is the input terminal for the current detection. Error amplifier compares the

lower one among 1/3 of the voltage terminal ADIM analog dimming and 1.0V(typ).

And it detects abnormal LED overcurrent at ISENSE=3.0V(typ) over. If GATE

terminal continues during four CLKs (equivalent to 40μs at fosc = 100kHz), it

becomes latch-off. (Please refer to section “3.5.7 Timing Chart”.)

ADIM[V]

0

3.0

1.0V

Gain=1/3

0.2

67mV

1.015V

3.3

Figure 13. Relationship of the feedback voltage and ADIM

Figure 14. ISENSE terminal circuit example

○Pin 12: GND

This is the GND pin of the IC.

　

]

k

[

]

kHz

[

f

R

SW

RT





15000

Figure 12. RT terminal circuit example

CH1:

STB

CH2:

REG50

CH3:

FAIL