BD9486F_16 datasheet(15/38 Pages) ROHM

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Datasheet

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TSZ02201-0F1F0C100240-1-2

15.Feb.2016 Rev.006

www.rohm.com

TSZ22111・15・001

BD9486F

●3.2.2 Shutdown Method and REG50 Capacitance Setting

When this IC shuts down, VOUT discharge function works. Indicated below is the sequence.

Figure 22. The waveform and diagram at shutdown

○Sequence explanation of shutdown

1. When STB=L, GATE and REG50 stop.

2. While STB=L and REG50UVLO=H, DIMOUT asserts the same logic of PWM. And VOUT is discharged until

REG50=5.0V reaches 2.3V by -5μA(typ.).

3. When VOUT is discharged enough by ILED, ILED doesn’t get to flow.

4. When REG50 voltage reaches under 2.3V(typ), whole system is shutdown.

○Setting method of REG50 capacitance

When REG50 terminal capacitance is defined as CREG , shutdown time TOFF is decided by the following equation.

When discharge function is used, PWM signal must be continuously inputted after STB=L.

VOUT discharge time is longest when PWM is set on mininum DUTY.

Please set CREG capacitance value with margin so that the system is shutdown after VOUT is discharged enough.

Please refer “1.6External Components Recommended Range” when setting CREG capacitance.

●3.2.3 VCC Series Resistance Setting

Here are the following effects of inserting series resistor Rvcc into VCC

line.

(i) In order to drop the voltage VCC, it is possible to suppress the heat

generation of the IC.

(ii) It can limit the inflow current to VCC line.

However, if resistance RVCC is set bigger, VCC voltage becomes under

minimum operation voltage (VCC<9V). RVCC must be set to an

appropriate series resistance.

Especially, after STB is set to High, IREG may become large and VCC

may fall greatly in the section charged to the capacitor of REG50

terminal depending on the external circuit of a VCC terminal.

Even in such a case, please set up to be set to VCC>9V in an operating

condition.

IC’s inflow current line I_IN has the following inflow lines.

・

IC’s circuit current…ICC

・

Current of RREG connected to REG50…IREG

・

Current to drive FET’s Gate…I_GATE

These decide the voltage ΔV at RVCC.

VCC terminal voltage at that time can be expressed as follows.

Here, judgement is the 9V minimum operation voltage.

Please consider a sufficient margin when setting the series resistor of VCC.



]

[

]

Ω

[

RVCC

]

[

IREG

]

[

IDCDC

]

[

ICC

]

[

VIN

[V]

VCC











Figure 23. VCC series resistance

circuit example

[sec]

]

[

]

[

)

(

]

[

REG

OFF









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