MCP8026 datasheet(34/64 Pages) MICROCHIP

34 / 64 page

MCP8025/6

DS20005339B-page 34

 2016 Microchip Technology Inc.

4.3.4.2

Gate Control Logic

The gate control logic provides level shifting of the

digital inputs, polarity control and cross conduction

protection.

4.3.4.2.1 Cross Conduction Protection

Logic prevents switching on one power MOSFET while

the opposite one in the same half-bridge is already

switched on. If both MOSFETs in the same half-bridge

are commanded ON simultaneously by the digital

inputs, both will be turned off.

4.3.4.2.2 Programmable Dead Time

The gate control logic employs a break-before-make

dead-time delay that is programmable. A configuration

message is provided to configure the driver dead time.

The programmable dead times range from 250 ns to

2000 ns (default) in 250 ns increments. The dead time

allows the PWM inputs to be direct inversions of each

other and still allow proper motor operation. The dead

time internally modifies the PWMH/L gate drive timing

to prevent cross conduction. The DRVDT<2:0> bits in

the CFG2 register are used to set the dead time value.

4.3.4.2.3 Programmable Blanking Time

A configuration message is provided to configure the

driver current limit blanking time. The blanking time

allows the system to ignore any current spikes that may

occur when switching the driver outputs. The allowable

blanking times are 500 ns, 1 µs, 2 µs and 4 µs

(default). The blanking time will start after the

dead-time circuitry has timed out.

The DRVBT<1:0>

bits in the CFG2 register are used to set the blanking

time value.

The blanking time affects the driver undervoltage

lockout. The driver undervoltage lockout latches the

external MOSFET undervoltage lockout fault if the

undervoltage condition lasts longer than the time

specified by the tDUVLO parameter. The tDUVLO

parameter takes into account the blanking time if

blanking is in progress.

4.4

Chip Enable (CE)

The Chip Enable (CE) pin allows the device to be

disabled by external control. The Chip Enable pin has

four modes of operation.

4.4.1

FAULT CLEARING STATE

The CE pin is used to clear any faults and re-enable the

driver. After toggling the CE pin low to high, the system

requires a minimum time period to re-enable and start

up all the driver blocks. The start-up time is

approximately 35 μs. The maximum pulse time for the

high-low-high transition to clear faults should be less

than 1 ms. If the high-low-high transition is longer than

1 ms, the device will start up from the Standby state.

Any fault status bits that are set will be cleared by the

low-to-high transition of the CE pin if, and only if, the

fault condition has ceased to exist. If the fault condition

still exists, the active fault status bit will remain active.

No additional fault messages will be sent for a fault that

remains active.

4.4.2

WAKE FROM SLEEP MODE

The CE pin is also used to awaken the device from the

Sleep mode state. To wake the device from a Sleep

mode state, the CE pin must be set low for a minimum

of 250 μs. The device will then wake up with the next

rising edge of the CE pin.

The LIN bus may be used to wake the device from the

Sleep mode state. When a LIN wake-up event is

detected on the LIN_BUS pin, the device will wake up.

The MCP8025 will wake up on the rising edge of the

bus after detecting a dominate state lasting > 150 µs

on the bus. The LIN Bus master must provide the

dominate state for > 250 µs to meet the LIN 2.2A

specifications.

TABLE 4-4:

ILIMIT_OUT FAULTS

Fault

DE2 Register

Overtemperature

0x85 0x02

Device Input Undervoltage

0x85 0x04

Driver Input Overvoltage

0x85 0x08

Device Input Overvoltage

0x85 0x10

Buck Regulator Output Undervoltage

0x85 0x80

External MOSFET Undervoltage

Lockout

0x86 0x04

External MOSFET Overcurrent

Detection

0x86 0x08

5V LDO Undervoltage Lockout

0x86 0x20

TABLE 4-5:

WARNINGS

Fault

DE2 Register

Temperature Warning

0x85 0x01

Buck Regulator Overcurrent

0x85 0x20

Buck Regulator Undervoltage

0x85 0x40

Brownout – Configuration Lost

0x86 0x10

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