LE25S161 datasheet(14/54 Pages) ONSEMI

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LE25S161

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9-1. Contents of each status register

9-1-1. RDY (bit 0)

The RDY register is for detecting the write (Program, Erase and Write Status Register) end. When it is "1", the device is in

a busy state, and when it is "0", it means that write is completed.

9-1-2. WEN (bit 1)

The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will not

perform the write operation even if the write command is input. If it is set to "1", the device can perform write operations

in any area that is not block-protected.

WEN can be controlled using the write enable (WREN) and write disable (WRDI). By inputting the write enable (WREN:

06h), WEN can be set to "1" by inputting the write disable (WRDI: 04h), it can be set to "0." In the following states, WEN

is automatically set to "0" in order to protect against unintentional writing.

• At power-on

• Upon completion of Erase (SSE, SE, or CHE)

• Upon completion of Page Program (PP or PPL)

• Upon completion of Write Status Register (WRSR)

* If a write operation has not been performed inside the LE25S161 because, for instance, the command input for any of

the write operations (SSE, SE, CHE, PP, PPL or WRSR) has failed or a write operation has been performed for a

protected address, WEN will retain the status established prior to the issue of the command concerned. Furthermore, its

state will not be changed by a read operation.

9-1-3. BP0, BP1, BP2, TB (bits 2, 3, 4, 5)

Block Protect: BP0, BP1, BP2 and TB are status register bits that can be rewritten, and the memory space to be protected

can be set depending on these bits. For the setting conditions, refer to "Table 4. Protected Level Setting Conditions".

BP0, BP1, and BP2 are used to select the protected area and TB to allocate the protected area to the higher-order address

area or lower-order address area.

Table 4. Protection Level Setting Conditions

Protected Level

Protected Block

Status Register Bits

Protected Area

BP2

BP1

BP0

Whole area unprotected

None

Upper side 1/32 protected

1F0000h to 1FFFFFh

Upper side 1/16 protected

1E0000h to 1FFFFFh

Upper side 1/8 protected

1C0000h to 1FFFFFh

Upper side 1/4 protected

180000h to 1FFFFFh

Upper side 1/2 protected

100000h to 1FFFFFh

Lower side 1/32 protected

000000h to 00FFFFh

Lower side 1/16 protected

000000h to 01FFFFh

Lower side 1/8 protected

000000h to 03FFFFh

Lower side 1/4 protected

000000h to 07FFFFh

Lower side 1/2 protected

000000h to 0FFFFFh

Whole area protected

000000h to 1FFFFFh

Note: Chip Erase is enabled only when the protection level is 0.

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