LE25S161 datasheet(23/54 Pages) ONSEMI

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LE25S161

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10-6-2. Dual I/O Read command (RDIO)

Maximum Clock frequency: 50MHz

The SI and SO pins change into the input/output pin (SIOx) during this operation. It makes the address input and data

output x2 bit and has achieved a high-speed output. Add1 (A23, A21, -, A3 and A1) is input from SIO1 and Add0 (A22,

A20, -, A2 and A0) is input from SIO0. bit7, 5, 3 and bit1are output from SIO0. bit6, 4, 2 and bit0 are output from SIO1.

"Figure 9. Dual I/O Read (RDIO)" shows the timing waveforms.

The sequence of RDIO operation :

CS goes to low  input RDIO command (BBh)

 3 Byte address (A23-A0) input on SI/SIO0 and SO/SIO1 by 12 clock cycle

 2 dummy clock (SI/SIO0 and SO/SIO1 are don’t care)

+ 2 dummy clock (must set SI/SIO0 and SO/SIO1 high impedance)

 the corresponding data out on SI/SIO0 and SO/SIO

 continuous data out (n-byte) per 4clock 

 completed by CS=high

* The data output starts from the falling edge of SCK(23th clock)

Input Address

Output Data

SI/SIO0

A22,20,18 --,A2,A0

bit6,4,2,0

SO/SIO1

A23,21,19 --,A3,A1

bit7,5,3,1

The Address is latched on rising edge of SCK. It is necessary to add 4 dummy clocks after address is latched,

2CLK of the latter half of the dummy clock is in the state of high impedance, the controller can switch I/O for this period.

The corresponding data is shifted out on SI/SIO0 and SO/SIO1 by the falling edge of SCK. The address is automatically

incremented to the next higher address after each byte data (4 clock cycles) is shifted out. If the SCK input is continued

after the internal address arrives at the highest address (1FFFFFh), the internal address returns to the lowest address

(000000h). By setting CS to high, the device is deselected, and the read cycle is completed. While the device is deselected,

the output pin SO is in a high-impedance state.

Figure 9. Dual I/O Read (RDIO)

● Address A23 to A21 are "Don't care".

DATA0: bit6,bit4,bit2,bit0

DATA1: bit7,bit5,bit3,bit1

High Impedance

DATA1

SCK

SIO1

SIO0

BBh

Add1:A22,A20-A2,A0

MSB

22 23 24

27 28

Mode3

Mode0

8CLK

MSB

Byte3

Byte2

Byte 1

DATA0

4CLK

dummy

bit

20 21

Add2:A23,A21-A3,A1

2CLK

12CLK

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