PCM2704,PCM2705

PCM2706,PCM2707

SLES081A − JUNE 2003 – REVISED MAY 2004

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24

MC

MS

MD

16-Bits

(1) Single Write Operation

MSB

LSB

MSB

(2) Continuous Write Operation

MSB

LSB

MSB

LSB

MSB

LSB

16-Bits x N Frames

MC

MS

MD

N Frames

Figure 27. SPI Write Operation

SPI REGISTER (PCM2705/7)

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

0

0

0

0

ST

0

ADDR

0

D0

D1

D2

D3

D4

D5

D6

D7

D[7:0]

Function of the lower 8 bits depends on the value of the ST (B11) bit.

ST = 0 (HID status write)

D7

Reports MUTE HID status to the host (active high)

D6

Reports volume-up HID status to the host (active high)

D5

Reports volume-down HID status to the host (active high)

D4

Reports next-track HID status to the host (active high)

D3

Reports previous-track HID status to the host (active high)

D2

Reports stop HID status to the host (active high)

D1

Reports play/pause HID status to the host (active high)

D0

Reports extended command status to the host (active high)

ST = 1 (ROM data write)

D[7:0] Internal descriptor ROM data

ADDR

Starts write operation for internal descriptor reprogramming (active high)

456 bits of ROM data, (described in the External ROM Example section) must be provided when this bit is asserted.

To set ADDR high, ST must be set low. Note that the lower 8 bits are still active when ST is set low.

ST

Determines the function of the lower 8-bit data as follows

0: HID status write

1: Descriptor ROM data write