PCM2704,PCM2705

PCM2706,PCM2707

SLES081A − JUNE 2003 – REVISED MAY 2004

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25

Functionality of ST and ADDR Bit Combinations

ST

ADDR

FUNCTION

0

0

HID status write

0

1

HID status write and descriptor ROM address read

1

0

Descriptor ROM data write

1

1

Reserved

USB HOST INTERFACE SEQUENCE

Power-On, Attach, and Playback Sequence

The PCM2704/5/6/7 is ready for setup when the reset sequence has finished and the USB bus is attached. After a

connection has been established by setup, the PCM2704/5/6/7 is ready to accept USB audio data. While waiting for

the audio data (idle state), the analog output is set to bipolar zero (BPZ).

When receiving the audio data, the PCM2704/5/6/7 stores the first audio packet, which contains 1 ms of audio data,

into the internal storage buffer. The PCM2704/5/6/7 starts playing the audio data after detecting the next subsequent

start-of-frame (SOF) packet.

D+/D−

2.0 V (Typ.)

0 V

Internal Reset

Ready for Setup

SOF

Ready for Playback

Bus Reset

Set Configuration

SOF

SOF

BPZ

Bus Idle

3.3 V

(Typ.)

1st Audio Data

2nd Audio Data

SSPND

VOUTL

VOUTR

700

µs

Device Setup

1 ms

VDD

Figure 28. Initial Sequence