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SC16C652 Datasheet(PDF) 17 Page - NXP Semiconductors |
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SC16C652 Datasheet(HTML) 17 Page - NXP Semiconductors |
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17 / 41 page ![]() Philips Semiconductors SC16C652 Dual UART with 32 bytes of transmit and receive FIFOs Product data Rev. 04 — 20 June 2003 17 of 41 9397 750 11634 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C652 in the FIFO polled mode of operation. In this mode, interrupts are not generated and the user must poll the LSR register for TX and/or RX data status. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). • LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO. • LSR[1-4] will provide the type of receive errors, or a receive break, if encountered. • LSR[5] will indicate when the transmit FIFO is empty. • LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty. • LSR[7] will show if any FIFO data errors occurred. 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the DMA mode. 7.3.1 DMA mode Mode 0 (FCR bit 3 = 0): Set and enable the interrupt for each single transmit or receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever the FIFO (THR, if FIFO is not enabled) is empty. Receive Ready (RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with a character. Mode 1 (FCR bit 3 = 1): Set and enable the interrupt in a block mode operation. The transmit interrupt is set when the transmit FIFO is below the programmed trigger level. The receive interrupt is set when the receive FIFO fills to the programmed trigger level. However, the FIFO continues to fill regardless of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long as the FIFO fill level is above the programmed trigger level. |
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