SC16C652 datasheet(20/41 Pages) PHILIPS

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Philips Semiconductors

SC16C652

Dual UART with 32 bytes of transmit and receive FIFOs

Product data

Rev. 04 — 20 June 2003

20 of 41

9397 750 11634

7.4 Interrupt Status Register (ISR)

The SC16C652 provides six levels of prioritized interrupts to minimize external

software interaction. The Interrupt Status Register (ISR) provides the user with four

interrupt status bits. Performing a read cycle on the ISR will provide the user with the

highest pending interrupt level to be serviced. No other interrupts are acknowledged

until the pending interrupt is serviced. A lower level interrupt may be seen after

servicing the higher level interrupt and re-reading the interrupt status bits. Table 14

“Interrupt source” shows the data values (bits 0-3) for the four prioritized interrupt

levels and the interrupt sources associated with each of these interrupt levels.

Table 14:

Interrupt source

Priority

level

ISR[5]

ISR[4]

ISR[3]

ISR[2]

ISR[1]

ISR[0]

Source of the interrupt

00110LSR (Receiver Line Status

00100

RXRDY (Received Data

Ready)

01100

RXRDY (Receive Data

time-out)

00010

TXRDY (Transmitter

Holding Register Empty)

00000

MSR (Modem Status

10000

RXRDY (Received Xoff

signal) / Special character

00000CTS, RTS change of state

Table 15:

Interrupt Status Register bits description

Bit

Symbol

Description

7-6

ISR[7-6]

FIFOs enabled. These bits are set to a logic 0 when the FIFOs are

not being used in the 16C450 mode. They are set to a logic 1

when the FIFOs are enabled in the SC16C652 mode.

Logic 0 or cleared = default condition.

5-4

ISR[5-4]

INT priority bits 4-3. These bits are enabled when EFR[4] is set to

a logic 1. ISR[4] indicates that matching Xoff character(s) have

been detected. ISR[5] indicates that CTS, RTS have been

generated. Note that once set to a logic 1, the ISR[4] bit will stay a

logic 1 until Xon character(s) are received.

Logic 0 or cleared = default condition.

3-1

ISR[3-1]

INT priority bits 2-0. These bits indicate the source for a pending

interrupt at interrupt priority levels 1, 2, and 3 (see Table 14).

Logic 0 or cleared = default condition.

ISR[0]

INT status.

Logic 0 = An interrupt is pending and the ISR contents may be

used as a pointer to the appropriate interrupt service routine.

Logic 1 = No interrupt pending (normal default condition).

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