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©2015 Integrated Device Technology, Inc

December 14, 2015

8312I Datasheet

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1, 5, 8, 12, 16,

17, 21, 25, 29

GND

Power

Power supply ground.

2, 7

Power

Positive supply pins.

3

CLK_EN

Input

Pullup

Synchronous control for enabling and disabling clock outputs.

LVCMOS / LVTTL interface levels.

4

CLK

Input

Pulldown

Single-ended clock input. LVCMOS/LVTTL interface levels.

6

OE

Input

Pullup

Output enable. Controls enabling and disabling of outputs Q[0:11].

LVCMOS / LVTTL interface levels.

9, 11, 13, 15,

18, 20, 22, 24,

26, 28, 30, 32

Q11, Q10, Q9, Q8,

Q7, Q6, Q5, Q4,

Q3, Q2, Q1, Q0

Output

Single-ended clock outputs. LVCMOS/LVTTL interface levels.

10, 14, 19, 23,

27, 31

Power

Output supply pins.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

4

pF

Input Pullup Resistor

51

k



51

k



Power Dissipation Capacitance

(per output); NOTE 1

19

pF

18

pF

16

pF

Output Impedance

7



7



10

