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8312AYILF Datasheet(PDF) 8 Page - Integrated Device Technology

Part # 8312AYILF
Description  Low Skew, 1-to-12 LVCMOS/LVTTL Fanout Buffer
PDF  18 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

8312AYILF Datasheet(HTML) 8 Page - Integrated Device Technology

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©2015 Integrated Device Technology, Inc
December 14, 2015
8312I Datasheet
Table 5C. AC Characteristics, VDD = VDDO = 1.8V ± 0.2V, TA = -40°C to 85°C
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Table 5D. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Parameter
Symbol
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
200
MHz
tpLH
Propagation Delay, Low to High; NOTE 1
ƒ
 200MHz
1.6
3.3
4.9
ns
tjit
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
0.172
ps
tsk(o)
Output Skew; NOTE 2, 5
160
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
2.4
ns
tR / tF
Output Rise/Fall Time; NOTE 5
20% to 80%
175
875
ps
odc
Output Duty Cycle
ƒ
 100MHz
45
55
%
Parameter
Symbol
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
250
MHz
tpLH
Propagation Delay, Low to High; NOTE 1
ƒ
 250MHz
1.5
2.1
2.8
ns
tjit
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
0.045
ps
tsk(o)
Output Skew; NOTE 2, 5
150
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
1ns
tR / tF
Output Rise/Fall Time; NOTE 5
20% to 80%
200
800
ps
odc
Output Duty Cycle
ƒ
 150MHz
45
55
%



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