TMS320DM642 datasheet(71/178 Pages) TI

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4.3

Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200J – JULY 2002 – REVISED AUGUST 2005

Case Temperature (Unless Otherwise Noted)

PARAMETER

TEST CONDITIONS (1)

MIN

TYP

MAX

UNIT

VOH

High-level output voltage (except PCI) DVDD = MIN, IOH = MAX

2.4

VOHP

High-level output voltage (PCI)

IOHP = –0.5 mA, DVDD = 3.3 V

0.9DVDD(2)

VOL

Low-level output voltage (except PCI)

DVDD = MIN, IOL = MAX

0.4

VOLP

Low-level output voltage (PCI)

IOLP = 1.5 mA, DVDD = 3.3 V

0.1DVDD(2)

VI = VSS to DVDD no opposing internal

±10

resistor

VI = VSS to DVDD opposing internal pullup

Input current (except PCI)

100

150

resistor (3)

VI = VSS to DVDD opposing internal

–150

–100

–50

pulldown resistor (3)

IIP

Input leakage current (PCI) (4)

0 < VIP < DVDD = 3.3 V

±10

EMIF, CLKOUT4, CLKOUT6, EMUx

–16

Video Ports, Timer, TDO, GPIO

IOH

High-level output current

–8

(Excluding GP0[15:9, 2, 1]), McBSP

PCI/HPI

–0.5(2)

EMIF, CLKOUT4, CLKOUT6, EMUx

Video Ports, Timer, TDO, GPIO

(Excluding GP0[15:9, 2, 1]), McBSP

IOL

Low-level output current

SCL0 and SDA0

PCI/HPI

1.5(2)

IOZ

Off-state output current

VO = DVDD or 0 V

±10

CVDD = 1.4 V, CPU clock = 720 MHz

1090

ICDD

Core supply current(5)

CVDD = 1.4 V, CPU clock = 600 MHz

890

CVDD = 1.2 V, CPU clock = 500 MHz

620

DVDD = 3.3 V, CPU clock = 720 MHz

210

IDDD

I/O supply current(5)

DVDD = 3.3 V, CPU clock = 600 MHz

210

DVDD = 3.3 V, CPU clock = 500 MHz

165

Input capacitance

Output capacitance

(1)

For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.

(2)

These rated numbers are from the PCI specification version 2.3. The DC specification and AC specification are defined in Table 5-3 and

Table 5-4, respectively.

(3)

Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.

(4)

PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs.

(5)

Measured with average activity (50% high/50% low power) at 25°C case temperature and 133-MHz EMIF for –600 and –720 speeds

(100-MHz EMIF for –500 speed). This model represents a device performing high-DSP-activity operations 50% of the time, and the

remainder performing low-DSP-activity operations. The high/low-DSP-activity models are defined as follows:

•

High-DSP-Activity Model:

–

CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;

L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)]

–

McBSP: 2 channels at E1 rate

–

Timers: 2 timers at maximum rate

•

Low-DSP-Activity Model:

–

CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles;

L2/EMIF EDMA: None]

–

McBSP: 2 channels at E1 rate

–

Timers: 2 timers at maximum rate

The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320DMx Power

Consumption Summary application report (literature number SPRA962).

Device Operating Conditions

TMS320DM642 Datasheet(PDF) 71 Page - Texas Instruments

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