TMS320DM642 datasheet(32/178 Pages) TI

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TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200J – JULY 2002 – REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

IPD/

TYPE(1)

DESCRIPTION

IPU(2)

NAME

NO.

HD31/AD31/MRCLK(3)

HD30/AD30/MCRS(3)

HD29/AD29/MRXER(3)

HD28/AD28/MRXDV(3)

HD27/AD27/MRXD3(3)

HD26/AD26/MRXD2(3)

HD25/AD25/MRXD1(3)

HD24/AD24/MRXD0(3)

Host-port data (I/O/Z) [default] or PCI data-address bus (I/O/Z) or EMAC

HD23/AD23(3)

transmit/receive or control pins

HD22/AD22/MTCLK(3)

As HPI data bus (PCI_EN pin = 0)

HD21/AD21/MCOL(3)

•

Used for transfer of data, address, and control

HD20/AD20/MTXEN(3)

•

Host-Port bus width user-configurable at device reset via a 10-k

Ω resistor

pullup/pulldown resistor on the HD5 pin:

HD19/AD19/MTXD3(3)

As PCI data-address bus (PCI_EN pin = 1)

HD18/AD18/MTXD2(3)

•

Used for transfer of data and address

HD17/AD17/MTXD1(3)

Boot Configuration:

HD16/AD16/MTXD0(3)

I/O/Z

•

HD5 pin = 0: HPI operates as an HPI16.

HD15/AD15(3)

(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining

HD14/AD14(3)

HD[31:16] pins are reserved pins in the high-impedance state.)

HD13/AD13(3)

•

HD5 pin = 1: HPI operates as an HPI32.

(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)

HD12/AD12(3)

HD11/AD11(3)

For superset devices like DM642, the HD31/AD31 through HD16/AD16 pins can

also function as EMAC transmit/receive or control pins (when PCI_EN pin = 0;

HD10/AD10(3)

MAC_EN pin = 1). For more details on the EMAC pin functions, see the Ethernet

HD9/AD9(3)

MAC (EMAC) peripheral section of this table and for more details on how to

configure the EMAC pin functions, see the device configuration section of this

HD8/AD8(3)

data sheet.

HD7/AD7(3)

HD6/AD6(3)

HD5/AD5(3)

HD4/AD4(3)

HD3/AD3(3)

HD2/AD2(3)

HD1/AD1(3)

AA1

HD0/AD0(3)

PCI command/byte enable 0 (I/O/Z).

PCBE0

I/O/Z

When PCI is disabled (PCI_EN = 0), this pin is tied-off.

PCI serial interface chip select (O).

XSP_CS

IPD

When PCI is disabled (PCI_EN = 0), this pin is tied-off.

XSP_CLK/MDCLK(3)

I/O/Z

IPD

PCI serial interface clock (O) [default] or MDIO serial clock input/output (I/O/Z).

PCI serial interface data in (I) [default].

XSP_DI

IPU

In PCI mode, this pin is connected to the output data pin of the serial PROM.

PCI serial interface data out (O) [default] or MDIO serial data input/output

XSP_DO/MDIO(3)

I/O/Z

IPU

(I/O/Z). In PCI mode, this pin is connected to the input data pin of the serial

PROM.

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