MCP37231 datasheet(3/144 Pages) MICROCHIP

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 2014-2016 Microchip Technology Inc.

DS20005322D-page 3

MCP37231/21-200 AND MCP37D31/21-200

Description

The MCP37231/21-200 is Microchip's baseline 16-/14-

bit 200 Msps pipelined ADC family, featuring built-in

high-order digital decimation filters, gain and offset

adjustment per channel and fractional delay recovery.

The MCP37D31/21-200 device family features digital

down-conversion and CW beamforming capability, in

addition to the features offered by the MCP37231/21-

200.

All devices feature harmonic distortion correction and

DAC noise cancellation that enable high-performance

specifications with SNR of 74.7 dBFS (typical), and

SFDR of 90 dBc (typical).

These A/D converters exhibit industry-leading low-

power performance with only 490 mW operation while

using the LVDS interface at 200 Msps. This superior

low-power operation coupled with high dynamic

performance makes these devices ideal for various

high-performance,

high-speed

data

acquisition

systems, including communications equipment, radar

and portable instrumentation.

The output decimation filter option improves SNR

performance up to 93.5 dBFS with the 512x decimation

setting. The digital down-conversion option, in

conjunction with the decimation and quadrature output

options, offers great flexibility in digital communication

system design, including cellular base-stations and

narrow-band communications. Gain, phase and DC

offset can be adjusted independently for each input

channel, allowing for simplified implementation of CW

beamforming

and

ultrasound

Doppler

imaging

applications.

These devices can have up to eight differential input

channels through an input MUX. The sampling rate is

up to 200 Msps when a single channel is used, or

25 Msps per channel when all eight input channels are

used.

In dual or octal-channel mode, the Fractional Delay

Recovery (FDR) feature digitally corrects the difference

in sampling instance between different channels, so

that all inputs appear to have been sampled at the

same time.

The device samples the analog input on the rising edge

of the clock. The digital output code is available after 28

clock cycles of data latency. Latency will increase if any

of the digital signal post-processing (DSPP) options are

enabled.

AutoSync mode offers a great design flexibility when

multiple devices are used in applications. It allows

multiple devices to sample input synchronously at the

same clock.

The differential full-scale analog input range is

programmable up to 2.975 VP-P. The ADC output data

can be coded in two's complement or offset binary

representation, with or without the data randomizer

option. The output data is available as full-rate CMOS

or Double-Data-Rate (DDR) LVDS. Additionally, a

serialized LVDS option is also available for the 16-bit

octal-channel mode.

These devices also include various features designed

to maximize flexibility in the user’s applications and

minimize system cost, such as a programmable PLL

clock, output data rate control and phase alignment

and programmable digital pattern generation. The

device’s operational modes and feature sets are

configured by setting up the user-programmable

registers.

The device is available in Pb-free VTLA-124 and

TFBGA-121 packages. The device operates over the

commercial temperature range of -40°C to +85°C.

Package Types

(a) VTLA-124 Package.

(b) TFBGA-121 Package.

Bottom View

Dimension: 9 mm x 9 mm x 0.9 mm

Bottom View

Dimension: 8 mm x 8 mm x 1.08 mm

Ball Pitch: 0.65 mm

Ball Diameter: 0.4 mm

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