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MCP37231 Datasheet(PDF) 57 Page - Microchip Technology |
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MCP37231 Datasheet(HTML) 57 Page - Microchip Technology |
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57 / 144 page ![]() 2014-2016 Microchip Technology Inc. DS20005322D-page 57 MCP37231/21-200 AND MCP37D31/21-200 I FIGURE 4-15: Simplified Block Diagram of Decimation Filters. TABLE 4-13: REGISTER CONTROL PARAMETERS FOR USING DECIMATION FILTERS Control Parameter Register Descriptions Decimation Filter Settings FIR_A<8:0> 0x7A, 0x7B Channel A FIR configuration for single- or dual-channel mode FIR_B<7:0> 0x7C Channel B FIR configuration for single- or dual-channel mode Output Data Rate and Clock Rate Settings(1) OUT_DATARATE<3:0> 0x02 Output data rate: Equal to decimation rate OUT_CLKRATE<3:0> 0x02 Output clock rate: Equal to decimation rate Output Clock Phase Control Settings(2) EN_PHDLY 0x64 Enable digital output phase delay when decimation filter is used DCLK_PHDLY_DEC<2:0> 0x64 Digital output clock phase delay control Digital Signal Post-Processing (DSPP) Function Block Settings EN_DSPP_2 = 1 0x79 Enable dual-channel decimation Note 1: The output data and clock rates must be updated when decimation rates are changed. 2: Output clock (DCLK) phase control is used when the output clock is divided by OUT_CLKRATE<3:0> bit settings. Stage 1A FIR Input DeMUX Stage 2A FIR Stage 2B FIR Stage 3A FIR Stage 3B FIR Output D2 Single D2 Dual Output D4 Dual Stage 9A FIR Stage 9B FIR Output D128 I/Q D4 Single D8 Single D512 Single Ch. A Ch. B Single-channel operation Single 2 2 2 2 2 2 2 (Note 1) (Note 2) (Note 3) Ch. Input Dual Ch. Input Input DeMUX Ch. A Ch. B Input for DDC MUX MUX MUX DDC I/Q filtering Output D256 Dual MUX Note 1: Stage 1A FIR is the first stage of the FIR A filter. 2: (a) Single-channel mode: Only Channel A is used and controlled by FIR_A<8:0>. (b) Dual-channel mode or I/Q filtering in DDC mode: Both Channel A and Channel B are used: Channel A is used for the first channel or I data, and Channel B is used for the second channel or Q data. 3: Maximum decimation rate: (a) When I/Q filtering in DDC mode is not used: 512x for single-channel and 256x for dual-channel mode. (b) I/Q filtering in DDC mode: 128x each for FIR_A<8:1> and FIR_B<7:0>. Dual-channel operation |
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