MCP37231 datasheet(87/144 Pages) MICROCHIP

87 / 144 page

MCP37231/21-200 AND MCP37D31/21-200

DS20005322D-page 87

 2014-2016 Microchip Technology Inc.

ADDRESS 0X04 – SPI SDO OUTPUT TIMING CONTROL

R/W-1

R/W-0

R/W-1

SDO_TIME

FCB<6:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

SDO_TIME: SPI SDO output timing control bit

SDO output at the falling edge of clock (Default)

SDO output at the rising edge of clock

bit 6-0

FCB<6:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.

ADDRESS 0X07 – OUTPUT RANDOMIZER AND WCK POLARITY CONTROL

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

POL_WCK

EN_AUTOCAL_-

TIMEDLY

FCB<4:0>

EN_OUT_RANDOM

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

POL_WCK: WCK polarity control bit(1)

Inverted

Not inverted (Default)

bit 6

EN_AUTOCAL_TIMEDLY: Auto-calibration starter time delay counter control bit(2)

Enabled (Default)

Disabled

bit 5-1

FCB<4:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.

bit 0

EN_OUT_RANDOM: Output randomizer control bit

Enabled: ADC data output is randomized

Disabled (Default)

Note

See Address 0x68 (Register 5-26) for WCK/OVR pair control.

This bit enables the AUTOCAL_TIMEDLY<7:0> settings. See Address 0x1E (Register 5-6).

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