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AD9363ABCZ Datasheet(PDF) 6 Page - Analog Devices

Part # AD9363ABCZ
Description  Radio frequency (RF) 2 횞 2 transceiver with integrated 12-bit DACs and ADCs
PDF  32 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9363ABCZ Datasheet(HTML) 6 Page - Analog Devices

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AD9363
Data Sheet
Rev. D | Page 6 of 32
Parameter1
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
Receiver Differential Input
Impedance
100
Ω
Logic Outputs
Output Voltage High
1375
mV
Output Voltage Low
1025
mV
Output Differential
Voltage
150
mV
Programmable in 75 mV steps
Output Offset Voltage
1200
mV
GENERAL-PURPOSE OUTPUTS
Output Voltage High
VDD_GPO × 0.8
VDD_GPO
V
Output Voltage Low
0
VDD_GPO × 0.2
V
Output Current
10
mA
SPI TIMING
VDD_INTERFACE = 1.8 V
SPI_CLK
Period
tCP
20
ns
Pulse Width
tMP
9
ns
SPI_EN Setup to First
SPI_CLK Rising Edge
tSC
1
ns
Last SPI_CLK Falling Edge to
SPI_ENB Hold
tHC
0
ns
SPI_DI
Data Input Setup to
SPI_CLK
tS
2
ns
Data Input Hold to
SPI_CLK
tH
1
ns
SPI_CLK Rising Edge to
Output Data Delay
4-Wire Mode
tCO
3
8
ns
3-Wire Mode
tCO
3
8
ns
Bus Turnaround Time, Read
(Master)
tHZM
tH
tCO (MAX)
ns
After baseband processors
(BBP) drives the last address bit
Bus Turnaround Time, Read
(Slave)
tHZS
0
tCO (MAX)
ns
After AD9363 drives the last
data bit
DIGITAL DATA TIMING (CMOS),
VDD_INTERFACE = 1.8 V
DATA_CLK_x Clock Period
tCP
16.276
ns
61.44 MHz
DATA_CLK_x and FB_CLK_x
Pulse Width
tMP
45% of tCP
55% of tCP
ns
Tx Data
TX_FRAME_x, P0_Dx, and
P1_Dx
Setup to FB_CLK_x
tSTX
1
ns
Hold to FB_CLK_x
tHTX
0
ns
DATA_CLK_x to Data Bus
Output Delay
tDDRX
0
1.5
ns
DATA_CLK_x to
RX_FRAME_x Delay
tDDDV
0
1.0
ns
Pulse Width
ENABLE
tENPW
tCP
ns
TXNRX
tTXNRXPW
tCP
ns
FDD independent enable state
machine (ENSM) mode
TXNRX Setup to ENABLE
tTXNRXSU
0
ns
TDD ENSM mode
Bus Turnaround Time
TDD mode
Before Rx
tRPRE
2 × tCP
ns
After Rx
tRPST
2 × tCP
ns
Capacitive Load
3
pF
Capacitive Input
3
pF



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