AD9363ABCZ datasheet(30/32 Pages) AD

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AD9363

Data Sheet

Rev. D | Page 30 of 32

SPI INTERFACE

The AD9363 uses a serial peripheral interface (SPI) to communi-

cate with the BBP. The SPI can be configured as a 4-wire interface

with dedicated receive and transmit ports, or it can be configured

as a 3-wire interface with a bidirectional data communication

port. This bus allows the BBP to set all device control parameters

using a simple address data serial bus protocol.

Write commands follow a 24-bit format. The first six bits set the

bus direction and number of bytes to transfer. The next 10 bits set

the address where data is to be written. The final eight bits are the

data to be transferred to the specified register address (MSB to

LSB). The AD9363 also supports an LSB first format that allows

the commands to be written in LSB to MSB format. In this mode,

the register addresses are incremented for multibyte writes.

Read commands follow a similar format with the exception that

the first 16 bits are transferred on the SPI_DI pin, and the final

eight bits are read from the AD9363, either on the SPI_DO pin

in 4-wire mode or on the SPI_DI pin in 3-wire mode.

CONTROL PINS

Control Outputs (CTRL_OUT7 to CTRL_OUT0)

The AD9363 provides eight simultaneous real-time output

signals for use as interrupts to the BBP. These outputs can

be configured to output a number of internal settings and

measurements that the BBP uses when monitoring trans-ceiver

performance in different situations. The control output pointer

the control output enable register determines which signals are

activated for monitoring by the BBP. Signals used for manual

gain mode, calibration flags, state machine states, and the ADC

output are among the outputs that can be monitored on these

pins.

Control Inputs (CTRL_IN3 to CTRL_IN0)

The AD9363 provides four edge detected control input pins. In

manual gain mode, the BBP uses these pins to change the gain

table index in real time.

GPO PINS (GPO_3 TO GPO_0)

The AD9363 provides four 3.3 V capable general-purpose logic

output pins: GPO_3, GPO_2, GPO_1, and GPO_0. These pins

control other peripheral devices such as regulators and switches

via the AD9363 SPI bus, or they function as slaves for the

internal AD9363 state machine.

AUXILIARY CONVERTERS

AUXADC

The AD9363 contains an auxiliary ADC that monitors system

functions such as temperature or power output. The converter is

12 bits wide and has an input range of 0.05 V to VDDA1P3_BB −

0.05 V. When enabled, the ADC is free running. SPI reads

provide the last value latched at the ADC output. A multiplexer in

front of the ADC allows the user to select between the AUXADC

input pin and a built-in temperature sensor.

AUXDAC1 and AUXDAC2

The AD9363 contains two identical auxiliary DACs that can

provide power amplifier (PA) bias or other system functionality.

The auxiliary DACs are 10 bits wide, have an output voltage range

of 0.5 V to VDD_GPO − 0.3 V and a current drive of 10 mA, and

can be directly controlled by the internal ENSM.

POWERING THE AD9363

The AD9363 must be powered by the following three supplies:

the analog supply (VDDx = 1.3 V), the interface supply (VDD_

INTERFACE = 1.8 V), and the GPO supply (VDD_GPO = 3.3 V).

For applications requiring optimal noise performance, split and

source the 1.3 V analog supply from low noise, low dropout

(LDO) regulators. Figure 42 shows the recommended method.

Figure 42. Low Noise Power Solution for the AD9363

For applications where board space is at a premium, and

optimal noise performance is not an absolute requirement,

provide the 1.3 V analog rail directly from a switcher, and adopt

a more integrated power management unit (PMU) approach.

Figure 43 shows this approach.

Figure 43. Space Optimized Power Solution for the AD9363

3.3V

1.8V

1.3V_A

1.3V_B

ADP2164

ADP1755

LDO

ADP5040

1.2A

BUCK

300mA

LDO

300mA

LDO

AD9363

1.3V

VDDx

1.8V

VDD_INTERFACE

3.3V

VDD_GPO

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