AD9363ABCZ datasheet(19/32 Pages) AD

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Data Sheet

AD9363

Rev. D | Page 19 of 32

Pin No.

Type1

Mnemonic

Description

J12

I/O

P1_D1/RX_D0_P

Digital Data Port 1, Data Bit 1/Receive Differential Output Bus, Data Bit 0. This is a

dual function pin. As P1_D1, it functions as part of the 12-bit bidirectional parallel

CMOS level Data Port 1. Alternatively, as RX_D0_P, it functions as part of the LVDS 6-

bit Rx differential output bus with internal LVDS termination.

K1, L1

RX1C_P, RX1C_N

Receive Channel 1 Differential C Inputs. Alternatively, use each pin as a single-ended

input. Tie unused pins to ground.

VDDA1P3_TX_SYNTH

Transmitter Synthesizer 1.3 V Supply Input. Connect this pin to a 1.3 V regulator

through a separate trace to a common supply point.

VDDA1P3_BB

Baseband 1.3 V Supply Input. Connect this pin to a 1.3 V regulator through a

separate trace to a common supply point.

RESET

Asynchronous Reset Input. A logic low resets the device.

SPI_EN

SPI Enable. Set this pin to logic low to enable the SPI bus.

I/O

P1_D8/RX_D4_N

Digital Data Port 1, Data Bit 8/Receive Differential Output Bus, Data Bit 4. This is a

dual function pin. As P1_D8, it functions as part of the 12-bit bidirectional parallel

CMOS level Data Port 1. Alternatively, as RX_D4_N, it functions as part of the LVDS 6-

bit Rx differential output bus with internal LVDS termination.

I/O

P1_D6/RX_D3_N

Digital Data Port 1, Data Bit 6/Receive Differential Output Bus, Data Bit 3. This is a

dual function pin. As P1_D6, it functions as part of the 12-bit bidirectional parallel

CMOS level Data Port 1. Alternatively, as RX_D3_N, it functions as part of the LVDS 6-

bit Rx differential output bus with internal LVDS termination.

I/O

P1_D4/RX_D2_N

Digital Data Port 1, Data Bit 4/Receive Differential Output Bus, Data Bit 2. This is a

dual function pin. As P1_D4, it functions as part of the 12-bit bidirectional parallel

CMOS level Data Port 1. Alternatively, as RX_D2_N, it functions as part of the LVDS 6-

bit Rx differential output bus with internal LVDS termination.

K10

I/O

P1_D2/RX_D1_N

Digital Data Port 1, Data Bit 2/Receive Differential Output Bus, Data Bit 1. This is a

dual function pin. As P1_D2, it functions as part of the 12-bit bidirectional parallel

CMOS level Data Port 1. Alternatively, as RX_D1_N, it functions as part of the LVDS 6-

bit Rx differential output bus with internal LVDS termination.

K11

I/O

P1_D0/RX_D0_N

Digital Data Port 1, Data Bit 0/Receive Differential Output Bus, Data Bit 0. This is a

dual function pin. As P1_D0, it functions as part of the 12-bit bidirectional parallel

CMOS level Data Port 1. Alternatively, as RX_D0_N, it functions as part of the LVDS 6-

bit Rx differential output bus with internal LVDS termination.

RBIAS

Bias Input Reference. Connect this pin through a 14.3 kΩ (1% tolerance) resistor to

ground.

AUXADC

Auxiliary ADC Input. If this pin is unused, tie it to ground.

SPI_DO

SPI Serial Data Output in 4-Wire Mode, High-Z in 3-Wire Mode.

M1, M2

RX1A_P, RX1A_N

Receive Channel 1 Differential A Inputs. Alternatively, use each pin as a single-ended

input. Tie unused pins to ground.

TX_MON1

Transmit Channel 1 Power Monitor Input. If this pin is unused, tie it to ground.

M7, M8

TX1A_P, TX1A_N

Transmit Channel 1 Differential A Outputs. Tie unused pins to 1.3 V.

M9, M10

TX1B_P, TX1B_N

Transmit Channel 1 Differential B Outputs. Tie unused pins to 1.3 V.

M12

XTALN

Reference Frequency Connection. Connect the external clock source to XTALN.

1 I is input, NC is not connected, GND is ground, O is output, P is power, and I/O is input/output.

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